Articles
- Crystal, oscillator or ceramic resonator: which clock?
A crystal is ±120 ppm over ten years, a ceramic resonator ±1.1 %, an RC oscillator ±2 %, and each is right for something. What UART, USB and a radio need.
- Oscilloscope probes: 10:1, and why the ground lead rings
A probe is a circuit, not a wire: 10 MΩ and 11 pF, a 117 nH ground lead, and a bandwidth of its own. An 11 pF probe on a 6-inch clip rings at 140 MHz.
- Level shifters: one MOSFET per line, or a translator IC
A 3.3 V device and a 5 V device can share a line safely. For open-drain buses one MOSFET per line does it, with no direction pin: AN10441's circuit.
- SPI vs I2C: which is faster, and why the answer is both
SPI is faster because nothing caps its clock and it spends 8 clocks per byte; I2C spends 9 and stops at 3.4 Mbit/s. Four reasons the choice is not about speed.
- Pull-up vs pull-down resistors: which one, and what value
Which direction, and what value: top set by leakage and bottom by the driver's sink current, 1.8 kΩ to 727 kΩ in TI's case, which is why 10 kΩ works.
- Dropout voltage: why the datasheet number is not yours
Dropout is a resistance times your load, not a figure: TI's 160 mV at 200 mA is 0.8 Ω, so 100 mA drops 80 mV. Where it comes from, and how to check headroom.
- Switch debounce: the RC, the Schmitt trigger and the numbers
A switch bounces up to 10 ms; logic answers in nanoseconds. Würth's RC and a Schmitt input fix it, but the 1 µF crosses the SN74HC14's threshold mid-bounce.
- Inrush current limiter: sizing an NTC, or using a MOSFET
A discharged bulk capacitor is a short circuit at power-on. Sizing the NTC takes three numbers from Ametherm and TDK, and knowing when a MOSFET is better.
- Why a relay has a flyback diode, and why it slows release
A flyback diode gives the coil current a path, so the switch sees 12.7 V instead of hundreds. TE's note shows the cost: slow release, and welded contacts.
- ADC noise floor calculation: SNR, process gain and the FFT
An ideal 12-bit ADC has 74 dB of SNR; its 4096-point FFT shows a floor at 107 dB. Both are right, and the 33 dB between them is the commonest misreading.
- MOSFET gate resistor: what value, and what it actually sets
The gate resistor sets one thing, how fast the drain slews during the Miller plateau, and costs one thing in return. TI's design: 10.5 Ω for a 2.3 kV/µs edge.
- Reverse polarity protection: diode, MOSFET or ideal diode?
A Schottky costs 0.4 V and 4.65 W at 10 A; a P-channel MOSFET costs 35 mV but lets holdup capacitors drain backwards; an ideal-diode controller does neither.
- AWG wire gauge and current: what actually sets the limit
Why a wire's current rating belongs to its insulation rather than its copper, what the ampacity charts really measure, and why voltage drop usually binds first.
- USB 2.0 layout: 90 Ω differential, and where the TVS goes
The impedance, the length match, the capacitance budget and the order of the protection parts — with the numbers and the documents each one comes from.
- Resistor codes: colour bands, SMD digits and EIA-96
How to read every resistor marking, why the E-series values look arbitrary, and which codes are genuinely ambiguous — with the tolerance derived, not looked up.
- Switch-node ringing: measure it, then size the snubber
Two scope readings give the loop inductance and the parasitic capacitance. From those the snubber values follow, and so does the reason to fix the layout first.
- Choosing a buck inductor: ripple, saturation and heat
Size the inductance from the ripple target, then check the peak against saturation and the RMS against heating — two different ratings that fail differently.
- How much current melts a PCB trace
Onderdonk's equation, where it stops being true, how it compares against IPC's continuous rating, and why a resettable fuse can be slower than the copper.
- How long will the battery last? Estimating it properly
Capacity over average current is the easy part. Here is what the cell's rated drain, its internal resistance and the cutoff voltage do to that answer.
- UART baud rate error: how much you can get away with
Why 2 % per end is the limit, where 8.5 % errors come from, what the odd crystal values buy, and what a fractional baud divider costs you in return.
- Sallen-Key low-pass filter design, without the guesswork
Pick a response shape, read its Q, and get the two capacitors and one resistor. Then the four things that decide whether the built filter matches the design.
- Measuring supply ripple: the ground clip is the antenna
A 3-inch probe ground lead turns a switching spike into ringing that is not on the rail. Tip-and-barrel, coax, bandwidth limits, and the null test.
- LED series resistor: the value, and the current you get
Compute the resistor from headroom, then find why one part number gives a 2:1 current spread on 3.3 V, what an MCU pin really delivers, and when to stop.
- 555 astable design: frequency, duty cycle and error
Size RA, RB and C for a 555 oscillator, find out why the duty cycle cannot reach 50 %, and see which of the datasheet's error terms actually dominates.
- Guard rings: stopping PCB leakage into high-impedance nodes
Gigaohm trace-to-trace resistance still leaks nanoamps at 5 V. Compute when board leakage beats V_OS and bias current, and lay out a driven guard to remove it.
- How to terminate a clock line: series, parallel or nothing
When a clock line needs no termination, when one series resistor at the driver is enough, and the exact networks LVDS, LVPECL and HCSL clocks need.
- How many thermal vias, and when more stop helping
One 12-mil via is 261 °C/W, sixteen under the pad are 16 °C/W, and the fortieth buys almost nothing. Size the array, the pad and the copper from TI's data.
- How a common-mode choke works, and where it goes on USB
How coupled windings block common-mode noise but pass the differential signal, how to read both impedance curves, and where the choke and TVS go on USB 2.0.
- Buck converter input filter design for conducted EMI
Size a buck converter's LC input filter from the required attenuation at the switching fundamental, damp the resonant peak, and keep the control loop stable.
- Buck converter PCB layout: find the hot loop first
The two switch-state current loops differ by one small loop carrying chopped current. Its area sets the EMI, and the input capacitor's placement sets its area.
- Why an LDO oscillates: the output capacitor's ESR tunnel
The ESR zero that keeps a PMOS LDO stable, the tunnel where too little and too much both oscillate, why ceramics broke old parts, and what C_NR and C_FF trade.
- How to choose and place a TVS diode for ESD protection
Why a 5 V TVS hands the pin 10 V mid-strike, which datasheet numbers predict it, and the placement rules that stop loop inductance adding 40 V per nanohenry.
- Should you split analog and digital ground planes?
One continuous ground plane with partitioned placement beats a split: where return current really flows, where AGND and DGND tie, and when a moat is right.
- I2C pull-up resistors: the value is a window, not a number
Size an I²C pull-up from both ends: Rp(min) from the 3 mA sink limit, Rp(max) from rise time and bus capacitance — with the worked window at 3.3 V, 200 pF.
- Bringing up a board that does nothing
A first-power-on procedure in the order that finds faults fastest: current before voltage, rails before reset, reset before clock, clock before code.
- Your 2.2 µF is 0.68 µF: DC bias and the capacitance you did not buy
Ceramics lose capacitance under DC voltage. Würth measured a 25 V X7R part losing 69 % of its value at its rated voltage, and the datasheet never mentions it.
- Ferrite beads are not resistors, and the 100 Ω is not 100 Ω
A bead is useful in the middle of its curve, the rated impedance is one point at 100 MHz, DC bias collapses it, and before a capacitor it can amplify noise.
- Reflections you can see: when a trace becomes a transmission line
The rule is not length, it is rise time. TI's rule is four times the one-way delay: below it a trace is a wire, above it each unterminated end is a mirror.
- RS-485 termination: when 120 Ω helps and when it just costs you
Where the 120 Ω comes from, the loop-time test that decides if you need it, AC termination as a data-rate trade, and how failsafe bias eats your node budget.
- The via is the decoupling: 40 dB from layout alone
Würth built one board with the same ferrite and the same two 100 nF capacitors in every channel, and changed only the layout. The worst channel is 40 dB down.
- θJA is a property of the test board, not of your board
The thermal resistance on the datasheet was measured on a JEDEC board that is not yours. What the number actually contains, and the five terms you control.
- Where the buck ripple comes from, and why more capacitance didn't help
The textbook ΔV = I/(8Cf) is the special case where ESR is zero. Where most real designs sit, output ripple is I·ESR, independent of capacitance and frequency.
- Why 100 nF, and the frequency where it stops being a capacitor
The value is inherited, not derived. What decides if a decoupling capacitor works is its inductance, and above a few tens of megahertz 100 nF is an inductor.
- Why the crystal won't start
A Pierce oscillator fails in a few ways: too little gain for the crystal's ESR, too much drive, wrong load capacitance, or stray capacitance. Each has a test.