USB 2.0 layout: 90 Ω differential, and where the TVS goes

The impedance, the length match, the capacitance budget and the order of the protection parts — with the numbers and the documents each one comes from.

USB 2.0 is forgiving compared with what came after it, and that is exactly why it gets laid out carelessly. The rules that matter are few and numeric:

90 Ω ± 15 % differential           TI SLLU149, Würth ANP024
length matched within 25 mil       SLLU149's layout drawings
matched at the device end          SLLU149, explicitly
under 5 pF of added capacitance    Würth ANP002
connector → TVS → choke → chip     ANP002

Everything below is where those numbers come from, what each one is worth in picoseconds or picofarads, and which of them actually decides whether the link works. The microstrip impedance calculator turns the first into a trace geometry and the TVS clamping calculator checks the fourth against what the protected pin can survive.

The signal path from a USB connector to the controller: the differential pair passes a TVS array and then a common-mode choke, while VBUS passes a ferrite bead, a capacitor and a second bead. — Fig 1 — The order Würth ANP002 recommends, and the order matters. The TVS array sits closest to the connector so the discharge never reaches the choke; the choke then filters what is left. VBUS gets its own chain, which is the part ANP002 says "a lot of design engineers forget … and wonder themselves when their product doesn't pass all the tests in EMI lab".

Where 90 Ω comes from, and how to get it

The number is a property of the cable, not the board. Würth’s ANP024 (The USB Interface from an EMC Point of View) puts it plainly: the cable impedance “must be 90 Ω +/-15% (symmetrical / differential)”, which is 45 Ω from each conductor to ground. The board’s job is to present the same thing so the connector is not a discontinuity.

TI’s SLLU149 (TUSB73x0 Board Design and Layout Guidelines) repeats it as a design rule — “the differential pair traces should be routed with 90 Ω ±15% differential impedance” — and that tolerance is generous. 76.5 Ω to 103.5 Ω is a window a fab can hold without a controlled-impedance quote, though asking for one costs little and removes the argument.

Getting there is a stackup question before it is a routing question. Using the IPC-2141 edge-coupled form the impedance calculator implements, on FR-4 with 1 oz copper: 12 mil traces with a 10 mil gap over an 8 mil dielectric gives 91.7 Ω. Halve the dielectric height and the same impedance needs roughly half the trace width, which is why a thin four-layer stackup makes USB harder rather than easier.

Contours of 90-ohm differential impedance in the plane of trace width against edge-to-edge spacing, drawn for three dielectric heights. Thinner dielectrics need narrower traces and closer spacing. — Fig 2 — Every trace width and gap that gives 90 Ω differential on FR-4, from the IPC-2141 edge-coupled form the impedance calculator uses. The dielectric height decides the whole family: on a 4-layer board with 8 mil to the plane, 12 mil traces with a 10 mil gap lands at 92 Ω; on a thin 4 mil prepreg the same impedance needs about 6 mil traces.

Length matching is worth less than you think

This is the rule that gets the most attention and deserves the least. SLLU149 gives two different numbers — its section 5.3 says the “max trace length mismatch between high speed USB signal pairs should be no greater than 150 mils”, while its layout drawings specify 25 mils — and both are comfortable.

Converting to time settles it. On FR-4 microstrip the propagation delay works out at 140 ps per inch, so a mil of mismatch is 0.14 ps:

  5 mil   0.7 ps    0.03 % of a bit    (the SuperSpeed rule)
 25 mil   3.5 ps    0.17 %             (SLLU149's drawings)
150 mil  21.0 ps    1.01 %             (SLLU149's text)

A 480 Mbps bit is 2083 ps. Even the loose limit spends 1 % of it. Design to 25 mils because it costs nothing on a two-trace pair, but do not reroute a board over it — and note that the serpentine used to achieve it has its own cost in coupling and length, so an unnecessary one is a net loss.

What SLLU149 is unambiguous about is where:

Length matching must be done at the device side, not at the connector.

The mismatch being corrected originates in the package’s internal routing and in the escape from the BGA. Correcting it at the far end leaves the pair mismatched for the entire run in between, which is where the coupling that makes it a differential pair actually happens.

Length mismatch converted to timing skew and shown as a fraction of the bit period, with the two limits the application note gives marked and the SuperSpeed limit for comparison. — Fig 3 — What a length mismatch is worth in time. On FR-4 microstrip a mil of mismatch is about 0.14 ps, so SLLU149's 150 mil limit is 21 ps — about 1.0 % of a 480 Mbps bit. The same note's layout drawings say 25 mils, which is the number to design to: it costs nothing and leaves the budget for everything else.

Two routings of the same pair: one with the serpentine length-matching added next to the connector and one with it next to the controller, where the application note requires it. — Fig 10 — SLLU149 is specific about this: "Length matching must be done at the device side, not at the connector." The mismatch it is correcting originates inside the package and in the escape routing, so a serpentine at the far end leaves the pair unmatched for the whole run between.

The capacitance budget is the real constraint

Here is the number that decides the parts list. ANP002 (The Protection of USB Applications) gives the budget in one line:

Which maximum capacitance can you add to your data lines to pass the eye pattern test? → For USB 2.0 line capacitances up to 5 pF shouldn’t cause any trouble

Five picofarads of added capacitance on each data line. The question ANP002 is answering is what can be added to the line, so the budget is for the protection parts, the connector and whatever else is hung on the pair — not for the controller’s own pin capacitance, which belongs to the PHY and is not counted against it. A TVS array spends between 1 and 3 pF of the budget depending on the part chosen, and that is before the connector and the trace.

What it costs is computable. A shunt capacitance at the connector is charged through the driver impedance in parallel with the line — about 22.5 Ω for a 90 Ω differential pair — so it adds roughly $2.2RC$ of rise time to the edge:

1 pF     50 ps added
2 pF     99 ps
5 pF    248 ps  —  12 % of a bit period

Which is why 5 pF is a limit rather than a target, and why the difference between a 1 pF TVS array and a 3 pF one is a real engineering choice rather than a datasheet detail. ANP002’s own comparison table makes the point sharply: the parts it lists have channel-to-channel capacitances of 0.1 pF against a competitor’s 1.5 pF, in the same package.

A stacked bar of the capacitance added to a USB 2.0 data line by the protection and the connector — the TVS array, then the connector and trace — against the five picofarad budget the application note gives for capacitance added to the line. — Fig 4 — Where the capacitance budget goes. ANP002 states that "for USB 2.0 line capacitances up to 5 pF shouldn't cause any trouble", and a well-chosen TVS array spends 2 pF of it. The budget is for what is added to the line — the question ANP002 answers is what can be added — so the controller's own pin capacitance is not counted against it. The choice between a 1 pF part and a 3 pF one is therefore a choice about how much of the budget is left for everything else.

The extra rise time a shunt capacitance adds to the data edge, plotted against capacitance and expressed as a percentage of the bit period. Five picofarads adds about a quarter of a nanosecond. — Fig 5 — What that capacitance does to the edge. A shunt C at the connector is charged through the driver and line impedances in parallel — about 22.5 Ω for a 90 Ω differential pair — so it adds 2.2 RC of rise time. At 5 pF that is 248 ps against a 2083 ps bit, which is why 5 pF is a limit rather than a target.

Choosing the TVS on the number that matters

Low capacitance is necessary but it is not what the part is for. The figure of merit is the clamping voltage under a real discharge, and ANP002’s table 3 gives it for a 6 kV IEC 61000-4-2 contact discharge:

part               I/O clamp   VDD clamp   C_IN
WE-TVS 824 015       12 V        7.5 V     2 pF
competitor S         22 V       15.5 V     3 pF
WE-TVS 824 001       14 V        9 V       1 pF
competitor P         28 V       19 V       3 pF

Same package, same pin count, same nominal job — and close to a factor of two in what reaches the protected pin (12 V against 22 V, 14 V against 28 V on the data pin; more than two on the supply pin). That difference lands directly on the controller’s absolute maximum rating, which for a 3.3 V USB PHY is usually under 4 V on the data pins. Nothing in that table protects such a pin from seeing several times its rating during the event; what the TVS does is keep the energy and the duration low enough that the pin’s own on-die protection survives, which is why how to choose and place a TVS diode is about placement as much as about the part.

ANP002 also explains why the clamping numbers in a datasheet are measurable at all, which is worth reading if you have ever tried to verify one on a bench:

The absolute peak voltage and the spike voltages during the refractions are an indicator for better and worse protection, but you cannot indicate the definitive clamping voltage. And by the way, this is not a reliable and repeatable measurement!

The answer is transmission-line pulsing, which drives the device from a 50 Ω system with a defined rectangular current pulse and measures the voltage that results. That is the measurement behind every clamping figure worth quoting.

Published clamping voltages at a six kilovolt contact discharge for four TVS arrays, on the data pin and the supply pin, alongside their input capacitances. The lower-capacitance parts also clamp lower. — Fig 6 — Würth ANP002's table 3, as published: clamping voltage under a 6 kV IEC 61000-4-2 contact discharge. The spread between parts of the same package and the same nominal function is a factor of two, and it lands directly on whatever the protected pin can survive — which is the number the TVS selection is actually about.

Order: TVS first, then the choke

The protection goes closest to the connector and the filter goes behind it. ANP002’s recommended layout is explicit about the sequence — the pair is “routed from connector to TVS-Diode … and via a common mode choke … to the USB controller”.

The reason is that the choke is an inductor, and an inductor in the discharge path develops a large voltage across itself for a fast current transient — so placing it ahead of the TVS both stresses the choke and delays the clamp. The same argument applies to any series element: nothing goes between the connector and the protection device except the shortest possible trace.

The choke, and the number to ask for

A common-mode choke sits in a 90 Ω differential path without destroying it because it presents almost nothing to a differential signal. ANP024 gives the figures for the part it recommends: 90 Ω common mode at 100 MHz, and 6 Ω differential mode, with a DC resistance of 0.3 Ω and a rated current of 370 mA. Common-mode attenuation into 90 Ω is quoted as more than 10 dB at 100 MHz.

That 6 Ω is the number to check on any candidate part, and it is a manufacturing property rather than a design one: it comes from how closely the two windings are balanced. A choke with a poor differential-mode figure adds that impedance to the signal path and closes the eye. If a datasheet does not give it, that is informative.

Whether the choke is needed at all depends on the emissions the enclosure has to meet. ANP002 notes that Intel’s platform design guidelines recommend one; a fully shielded product with a short cable may not need it, and the footprint can be fitted with a pair of zero-ohm links until the EMC lab says otherwise. That is a cheap insurance policy and a common one.

The common-mode and differential-mode impedance of a USB common-mode choke compared as bars: ninety ohms to common-mode noise and six ohms to the signal itself. — Fig 7 — Why a common-mode choke can sit in a 90 Ω differential path without ruining it. ANP024 gives the WE-CNSW 744232090 as 90 Ω common mode at 100 MHz and 6 Ω differential mode — the signal, which is entirely differential, sees the small number. A choke whose windings are poorly balanced does not have that property, which is what "differential mode impedance" on a datasheet is telling you.

The reference plane matters more than the length match

Of all SLLU149’s rules, this is the one whose violation actually breaks links:

The differential signal pairs must not be routed over gaps in the power planes or ground planes. This causes impedance mismatches.

The return current for a high-frequency signal does not spread out across the plane — it concentrates directly under the trace, because that is the path of least inductance. A slot forces it to detour, which adds inductance, changes the pair’s impedance over the detour, and turns the loop into an efficient radiator at the frequencies the pair carries. The 150 mil mismatch limit is 21 ps, 1 % of a bit; a plane slot under an inch of pair is a discontinuity worth far more than that and it radiates as well.

The related rules follow from the same physics. Route the pair on an outer layer with the plane immediately beneath. Change layers as few times as possible, because each via moves the return current to a different plane and it has to get there somehow. SLLU149 prices that explicitly for its PCIe lanes — “each signal trace via reduces the maximum trace length by approximately 2 inches” against a 20-inch budget, so its own example of six vias leaves eight inches — and for the USB 2.0 pair asks only for “the minimum amount of vias possible” and a total length under eight inches, beyond which it says to contact TI. USB 2.0 is far more tolerant, but the ordering both rules imply is the same: route the pair first, before anything else competes for the space.

Seen from above: a differential pair crossing a slot in the reference plane, with the return current pushed out from under the pair to detour in the plane around the end of the slot, drawn beside the same pair over continuous copper where the return runs directly beneath. — Fig 8 — The rule SLLU149 states as "the differential signal pairs must not be routed over gaps in the power planes or ground planes", and why. The return current wants to run directly under the trace; a slot forces it sideways in the plane, around the end of the slot, which adds inductance, changes the impedance and turns the detour into a loop antenna at the frequencies the pair is carrying.

Two length budgets from the same application note. The PCIe pair starts at twenty inches and loses about two inches per via, so six vias leave eight; the USB 2.0 high-speed pair has a flat eight-inch limit with no via term, and SuperSpeed the same eight inches from its compliance channel. — Fig 9 — Two different budgets in SLLU149. For its PCIe lanes the pair starts at 20 inches and "each signal trace via reduces the maximum trace length by approximately 2 inches" — the note's own example is six vias leaving eight. For the USB 2.0 pair there is no via term at all: keep it under eight inches and "contact TI" beyond that, with "the minimum amount of vias possible". USB 2.0 is the more forgiving interface, but the ordering both rules imply is the same: route the pair first, on an outer layer, and spend vias only where nothing else will do.

VBUS is the half everyone leaves bare

ANP002 is unusually blunt about this:

But for outstanding EMI behaviour it is necessary to protect the power supply (VBUS) as well. A lot of design engineers forget this important point and wonder themselves when their product doesn’t pass all the tests in EMI lab.

Two separate jobs live on VBUS. Filtering, because the supply carries whatever the downstream device does back out along the cable, and the cable is a metre of antenna. ANP002 recommends a chip bead ferrite and then adds that “after the chip bead you may add a capacitor and a second chip bead as well to get the highest possible EMI suppression effect” — which is a pi filter, and which the ferrite filter calculator will size, including the resonance a bead and capacitor can create between them. Ferrite beads are not resistors covers why the bead’s impedance curve, its DC current derating and its self-resonance all matter here.

And protection, where VBUS has an advantage the data lines do not:

For power line protection it is not necessary to use a low cap ESD suppressor, you might prefer a standard SMD varistor which can withstand higher surges and higher transient energies.

There is no capacitance budget on a power rail, so the part can be chosen purely for energy handling. That is one of the few places in this interface where the obvious answer is also the right one.

The VBUS filter chain: a ferrite bead, a bulk capacitor and a second bead, forming a pi filter between the connector and the load, with a varistor for surge protection. — Fig 11 — The half of the interface most designs leave bare. ANP002 recommends a chip bead ferrite on VBUS and adds that "after the chip bead you may add a capacitor and a second chip bead as well to get the highest possible EMI suppression effect" — a pi filter. It also notes that VBUS does not need a low-capacitance protector, so a standard varistor with a higher energy rating is the better choice there.

The whole thing, as numbers

A card of the numeric rules for USB 2.0 layout: differential impedance and tolerance, length matching, where to match, maximum length, capacitance budget and the component order. — Fig 12 — Everything on this page as numbers, with the document each comes from. None of them is difficult; all of them are easier to satisfy before the placement is fixed than after.

Two closing observations about the order in which these bite. A 100 mil length mismatch is 14 ps out of a 2083 ps bit — it is not where a USB 2.0 link fails. A pair crossing a plane split, a 3 pF protection array chosen on price, or a connector shell whose ground return goes through the board instead of straight to the chassis are the failures the documents above are written against. Spend the attention accordingly.

And every one of these rules is cheaper before the placement is fixed. The pair should be routed first, from the connector to the controller, with the protection and the choke placed on the line it wants to take — not squeezed into whatever is left after the rest of the board is done.