PCB stackups: what each layer is for, 2 to 8 layers

A layer stackup is not a list of what goes where. It is a set of promises about where every signal’s return current will flow, how far a supply’s current has to travel to reach its plane, and which planes can see each other. Get the order right and most of the layout rules in the vendor notes take care of themselves; get it wrong and no amount of routing discipline recovers it, because the return path was decided when the layers were. This article is the example stackups three vendor notes give — TI’s SPRAAR7 for six, eight and ten layers, Microchip’s AN 18.6 for two and four, Xilinx’s XAPP623 for the spacing inside a plane pair — and the reasoning each attaches to them.

The one rule under all of them

SPRAAR7 states it for high-speed signals, and it is the rule for every signal that has an edge: “high-speed signals should be routed over a solid GND reference plane and not across a plane split or a void in the reference plane unless absolutely necessary. TI does not recommend high-speed signal references to power planes.” The reason is what the return current does when the plane is not there: “routing across a plane split or a void in the reference plane forces return high-frequency current to flow around the split or void”, with “excess radiated emissions from an unbalanced current flow”, “delays in signal propagation … due to increased series inductance”, “interference with adjacent signals” and “degraded signal integrity”. Every stackup below is an arrangement that gives each signal layer a ground plane next to it.

Where a crossing is unavoidable, the note’s remedy is a capacitor: “place stitching capacitors across the split to provide a return path for the high-frequency current … 1 µF or lower and placed as close as possible to the plane crossing”. Where a signal changes layers and therefore reference planes, “via-stitch both GND planes together … symmetrically within 200 mils (center-to-center, closer is better) of the signal transition vias”. And planes that are not meant to talk must not overlap: “ensure that planes that do not reference each other are not overlapped because this produces unwanted capacitance between the overlapping areas”, which “could pass RF emissions from one plane to the other”.

Six, eight and ten layers: TI’s examples

“TI recommends a PCB of at least six layers.” Read the six-layer column as three promises. The outer signal layers each sit directly on a ground plane, so anything routed on top or bottom — including the high-speed pairs, which the note wants “on the top or bottom layer of the PCB with an adjacent GND layer” and not in stripline — has its return under it. The two inner signal layers face each other with no plane between, which is why the footnote insists they be “routed directly adjacent … at a 90° offset to each other”: crossing at right angles is what keeps two unshielded signal layers from coupling. And the power layer is shared with ground and “may be split”, with the warning that “traces on adjacent planes do not cross splits”.

Eight layers adds a second ground plane so that the two inner signal layers gain a reference between them and the split power plane; ten layers gives power its own layer and a full ground under the bottom signals. The pattern is the same at every count: a signal layer is paid for with a plane, and the planes are ground unless they cannot be.

Four and two layers: Microchip’s

AN 18.6’s four-layer stack is the one most small boards use, and its description carries the discipline that makes it work. “Top (Layer 1) – Signal with ground plane except where noted. Layer 2 – Continuous ground plane. No signals should be routed on this layer. Layer 3 – Power planes with ground planes except where noted … Bottom (Layer 4) – Signal with ground plane except where noted.” The cost is on the bottom layer, whose reference is layer 3’s patchwork of power islands rather than a ground plane. The note’s fix is the same as SPRAAR7’s: “when signal traces are re-referenced to power island planes, decoupling capacitors (0.01 µF ceramic) are required between the ground plane and power plane”, placed “near the trace to enable short (direct) return current paths”. A bottom trace crossing a 3.3 V island is fine if a 10 nF capacitor gives its return a way back to ground within a few millimetres, and a problem if not.

Two layers is a compromise the note accepts rather than recommends: “Top (Layer 1) Signal with ground plane except where noted. Bottom (Layer 2) Ground plane and power islands. A limited number of slow speed signals may be routed on the bottom layer.” With no continuous plane, each trace has to be given its own return: “signal traces should be surrounded by ground or ground trace along at least one edge”, and that guard “should be connected to ground plane on this layer and decoupled to ground plane on top layer”. Two layers is a ground plane with holes in it, and the rules are about keeping the holes away from the signals.

Inside the plane pair: how close is close

A ground plane next to a power plane is not only a reference for the signals above it; the pair is the supply’s lowest-inductance path and a capacitor in its own right, and XAPP623 quantifies both. “Since power and ground planes are by definition a planar structure … inductance of planes can be described as ‘spreading inductance,’ and is specified in units of henries per square”, and “this is primarily determined by the thickness of the dielectric separating a power plane from its associated ground plane.”

Its consequences for the layer order are explicit. “It is best, wherever possible, to place V_CC planes directly adjacent to GND planes in the stackup. Facing V_CC and GND planes are sometimes referred to as ‘sandwiches’.” Which pair goes where matters: “power supplies with high transient current should have their associated V_CC planes close to the top surface … to decrease the distance in the vertical direction that currents travel through V_CC and GND vias”, and because “manufacturing constraints typically require the PCB stackup to be symmetrical about the center”, the designer “must determine which V_CC and GND plane pairs have high priority or carry high-frequency energy, and which pairs have low priority”. The thin pair is also what lets decoupling capacitors sit around a BGA rather than under it — “provided all V_CC planes have a Ground plane adjacent to them, separated by a dielectric less than 4 mils in thickness” — and SPRABV2 gives the same structure its high-frequency role: “two extra PCB planes, one power and one ground, that are separated by an extremely thin (<10 mils) layer of dielectric” whose capacitance “can be effective to 10+ GHz”.

Impedance is a stackup number

The dielectric between a signal layer and its plane sets the trace width for a given impedance, so the stackup fixes the geometry before routing starts. TI’s PHYTER guide gives the microstrip and stripline equations and the trade: microstrip needs “a solid ground plane … under the signal traces”, stripline “sandwiched between the ground/supply planes” has “lower EMI radiation and less noise coupling” at the cost of “lower propagation speed”. SPRAAR7 adds the subtlety that the dielectric is not one material: the glass weave at ε_r about 6 and the epoxy at about 3 give the two traces of a pair different velocities, so on fast pairs it rotates the routing “10° to 35° in relation to the underlying PCB fiber weave”. The microstrip impedance calculator turns the stackup’s heights into widths; the stackup drawing from the fabricator is the input, not a guess.

Choosing

• Two layers: slow signals only, ground on the bottom with power as islands, every signal bordered by ground. Not for a PHY, a switching regulator’s fast node, or anything with a differential pair.
• Four layers: signal, ground, power, signal. Route the fast signals on top over the continuous ground; treat the bottom as re-referenced and give every island crossing its 10 nF.
• Six layers: SPRAAR7’s minimum for high-speed interfaces. Fast pairs on the outer layers over ground; the inner signal pair crossed at 90°; the power plane split only where the traces above it do not cross the split.
• Eight and ten: the same pattern with more ground, so that every signal layer has a plane and power can be its own layer.
• Any count: the high-current, fast-transient supply’s plane pair nearest the parts that draw it, thin dielectric between power and ground, and no overlap between planes that do not belong together.

Sources

• TI, SPRAAR7J — High-Speed Interface Layout Guidelines, 2023. Reference planes, splits and stitching, overlapped planes, the fiber-weave skew, and table 3-1’s example stackups.
• Microchip (SMSC), AN 18.6 — Ethernet Physical Layer Layout Guidelines. The four-layer and two-layer stackups and the re-referencing capacitors.
• Xilinx, XAPP623 — Power Distribution System Design: Using Bypass/Decoupling Capacitors, 2005. Spreading inductance, table 1, plane sandwiches and layer order.
• TI, SPRABV2 — BGA decoupling and PDN design. Inter-plane capacitance.
• TI, SNLA079D — AN-1469 PHYTER Design & Layout Guide. Microstrip against stripline.