Tag
pcb layout
4 articles.
- Reflections you can see: when a trace becomes a transmission line
The rule is not length, it is rise time. TI's criterion is four times the one-way delay — below it a trace is a wire, above it every unterminated end is a mirror. With a lattice diagram for the ringing you are looking at.
- The via is the decoupling: 40 dB from layout alone
Würth built one board with the same ferrite and the same two 100 nF capacitors in every channel, and changed only the layout. The worst channel is more than 40 dB down on the next best. The capacitor was never the variable.
- θJA is a property of the test board, not of your board
The thermal resistance on the datasheet was measured on a JEDEC board that is not the one you designed. Here is what the number actually contains, and the five terms you control.
- Why the crystal won't start
A Pierce oscillator fails in a small number of ways: not enough gain for the crystal's ESR, too much drive, the wrong load capacitance, or a layout that adds stray capacitance where it does the most harm. Each has a test.