Guard rings: stopping PCB leakage into high-impedance nodes

The decision rule fits in one line: multiply the current your board can leak into a node by that node’s source impedance, and compare the result with the amplifier’s input error budget. If the board’s number is bigger, no op amp selection will fix the measurement — the node needs a guard: copper surrounding it, driven to the node’s own potential, so that no voltage difference remains to push current through the board’s parasitic resistance.

The numbers make the rule bite sooner than intuition says. TI’s guarding note (SCDA042) estimates trace-to-trace resistance on a PCB in the gigaohm range — and a gigaohm under a 5 V difference leaks 5 nA. Push 5 nA through a 1 MΩ source and the error is 5 mV, against op amps that specify offset voltages of 25 µV (SBOA590) and bias currents of picoamps. Above a few kilohms of source impedance, an unguarded board — not the amplifier — owns the error budget.

The resistor you did not place

Every conductor pair on a board is connected by something: the bulk resistance of the laminate, the dielectric between traces, and — usually far worse — the film sitting on the surface. SCDA042 lists the leakage sources plainly:

leakage paths can be formed from several sources including flux on the board, debris (surface leakages), electrical interferences, and of course the inherent board resistance and dielectrics between conductors

None of these appear in the netlist. The honest schematic of a high-impedance node has an extra resistor on it, from every nearby potential into the node, with a value you did not choose and cannot rely on — it changes with contamination, with humidity, and with time.

The mental correction that matters: this is not an “insulation quality” problem to be solved by buying better laminate. It is Ohm’s law across a voltage difference, and the only two handles are the resistance and the difference. The resistance tops out at whatever the dirtiest day of the board’s life allows. The difference can be driven to zero — that is the guard.

Gigaohms still leak nanoamps

The arithmetic deserves to be seen, because “gigaohm” sounds like a synonym for “open circuit” and is not. SCDA042 works the example:

Take the trace to trace resistance as an example. At just a 5 V potential difference between two traces on a PCB and using an estimated trace to trace resistance in the Gigaohm range, this would amount to nA’s worth of leakage just from this relatively small delta alone.

$$I_{leak} = \frac{\Delta V}{R_{leak}}$$

For scale, the reference lines in the figure are real device budgets from the two documents: TI’s TMUX1108 multiplexer specifies 3 pA of on-leakage at 25 °C (SCDA042), and the OPA205A precision op amp specifies ±0.5 nA of maximum bias current (SBOA590). A single gigaohm path under 5 V out-leaks the op amp by 10× and the multiplexer by more than three orders of magnitude. Selecting a femtoamp-input part and then routing its input past a 5 V rail is paying for a specification the board immediately discards.

Where it hurts: the high-impedance node

Leaked current only becomes voltage error by flowing through impedance, which is why the same 5 nA is invisible on a 50 Ω node and fatal on a pH front end. SCDA042 gives the conversion for a multiplexer feeding a high-impedance load:

$$V_{ERROR} = \left(R_{ON} + R_{SOURCE}\right) \cdot I_{LEAK}$$

When feeding into a high impedance node, the leakage current takes the path of least resistance, which is through the on-resistance and source-resistance path and induce an offset error that affects the measurement at the output.

The nodes that live in the dangerous right-hand half of that plot are the usual precision suspects: multiplexer inputs scanning slow sensors, integrator summing junctions, photodiode transimpedance inputs, and electrochemical probes. SBOA590 puts a pH sensor’s source resistance above 100 MΩ — where the unguarded 5 nA line reads half a volt. A resistive divider feeding an ADC lives on the same axis: its output impedance is R1 ∥ R2, which is the number the voltage divider tool reports as R_th, and a divider stiff enough to ignore microamp-scale loading can still be soft enough to feel nanoamps.

The same table thinking applies inside SCDA042’s own comparison: a TMUX1308 (1 nA on-leakage, 75 Ω on-resistance at 25 °C) produces only 75 nV of offset against its on-resistance alone — but at 125 °C, 800 nA against 270 Ω is 216 µV, before any source impedance is added. Leakage specifications are room-temperature numbers; the mechanism behind them roughly doubles every 10 °C (SBOA590 quotes silicon diode leakage doubling per 10 °C), so a budget that closes at 25 °C can be two or three orders of magnitude off at temperature.

The amplifier’s own errors: V_OS, I_B and I_OS

To decide whether the board matters, the amplifier’s own contribution has to be on the table first. SBOA590 models it as two mechanisms. Input offset voltage V_OS sits directly in series with the input — from 2 µV for the best zero-drift CMOS parts (OPA387) to 3 mV for a commodity bipolar (LM741), with “precision” conventionally meaning under 1 mV. Input bias current I_B is the second, and it is the one that interacts with impedance:

Input bias current is a DC current on op amp input terminals that converts to an offset voltage when it flows through the source resistance and/or feedback resistors.

$$V_{IB} = I_{BN}\,(R_F \parallel R_G) - I_{BP}\,R_S \qquad I_{OS} = I_{BP} - I_{BN}$$

SBOA590’s worked example puts numbers on it: an OPA205A (±0.5 nA I_B, ±0.4 nA I_OS, both maxima at 25 °C) with a 10 kΩ source and a 100 kΩ/1 kΩ feedback network produces a worst-case 6.70 µV of input-referred offset. Two practical notes ride along. First, the classic trick of matching R_S to R_F ∥ R_G only cancels bias current when the two inputs draw equal current — and SBOA590 is blunt that for most CMOS and many bipolar parts I_OS is comparable to I_B, so the honest fix is minimising both resistances, not balancing them. Second, technology sets the scale: bipolar inputs need nanoamps to microamps of base current, while CMOS and JFET inputs leak only through their ESD structures — picoamps or femtoamps at room temperature. An OPA392 specifies ±0.8 pA maximum at 25 °C. That is the class of part a guarded layout is built to deserve.

When the board dominates the budget

Now stack the three terms — offset voltage, bias current times source impedance, board leakage times source impedance — and watch who wins where.

With SCDA042’s 5 nA of unguarded leakage on the board, the crossover against a 25 µV offset budget (OPA192 maximum, from SBOA590’s table) sits at 5 kΩ of source impedance. Five kilohms. Everything to the right of that line — every sensor, divider, filter or reference network above a few kilohms — gets its error from the board first and the amplifier second. And because the leakage line is 10× the bias-current line at every impedance, upgrading the op amp moves the total not at all: the plot is the case for spending layout effort before component budget.

Temperature sharpens the same conclusion. The CMOS amplifier’s femtoamp advantage erodes at roughly 2× per 10 °C, because its bias current is the leakage of its ESD diodes — SBOA590 puts the rise at about 1000× between room temperature and 125 °C, and its example curve runs from about 200 fA to 500 pA across temperature, a factor of 2 500 — but the board’s 5 nA never was a femtoamp number, and flux residue’s impedance drifts with temperature and humidity in the wrong direction too.

The guard principle: remove the voltage, not the path

Since the resistance cannot be trusted, the guard attacks ΔV. SCDA042 states the whole mechanism in two sentences:

Guarding techniques implement active conductors that are at the same potential as the sensitive net and surround said net to create an extremely low leakage environment. With the guard ring and the net at the same potential, this effectively creates an incredibly small voltage delta between the trace and immediate surrounding area which drastically reduces the possibility of stray leakage currents leaking into this area of the PCB.

Note what the guard does not do: it does not stop the leakage. Current still flows from the 5 V neighbour, across the same contaminated surface, at the same nanoamp scale — but it terminates on the ring, whose driver supplies it without complaint. The node sits inside a region where every surface it could leak to is already at its own potential. I = ΔV / R with ΔV ≈ 0 is approximately zero for any R, which is precisely the property a contaminated surface needs: the guard keeps working when the board gets dirty, because its mechanism never depended on the board being clean.

Femtoamps through the same gigaohm

How close to zero is ΔV ≈ 0? Exactly as close as the guard driver holds it, which is why the driver’s offset voltage is the specification that matters.

The figure runs the arithmetic on the same 1 GΩ surface twice. From the rail to the guard, 3 V of difference drives 3 nA — into the guard’s low-impedance driver, where it does no harm. From guard to node, the only difference left is the buffer’s offset: with SCDA042’s recommended OPA397 at 60 µV, the current into the node is 60 fA — a 50,000:1 reduction, set entirely by the ratio of the two voltage differences. This is where femtoamp measurement becomes possible on an ordinary board: not by finding a teraohm laminate, but by arranging for the volts to appear only across copper that can absorb the consequences.

Driven guard or grounded ring

The tempting shortcut is to tie the ring to ground and skip the driver. For a node that sits at ground potential anyway, that is a driven guard for free. For any node that moves — an integrator output’s summing junction, a sensor bias point, a multiplexer input at signal potential — a grounded ring is a different circuit:

The grounded ring still intercepts the outside world, but it places the node’s full potential across the narrowest gap on the board — the gap to the ring itself, which the layout deliberately made small. The “protection” now leaks the node to ground through whatever the surface resistance of that gap happens to be. A driven guard puts nothing across that gap at all.

Grounded rings do have a legitimate job: shielding, where the threat is interference rather than leakage. The guard ring around a single-layer oscillator layout is grounded on purpose — it exists to give switching fields somewhere to terminate, and the oscillator’s loop is not a DC-precision node. The two constructions look identical in copper; they differ in what the ring is connected to, and mixing them up in a precision front end quietly installs the failure mode above.

The buffer that drives the guard

The driver has two requirements, both from SCDA042: it must hold the guard at the net’s potential (its offset is the residual ΔV, as computed above), and it must not itself load the node it copies — the buffer’s input becomes one more leakage path into the net, so it needs the same low-bias-current character as the measurement amplifier. SCDA042 recommends precision buffers by operating voltage: OPA397 (5.5 V, 60 µV offset), OPAx197 (36 V, 25 µV), OPA593 (85 V, 10 µV), OPA455 (150 V, 3.4 mV).

Low output impedance is not a luxury here. The guard absorbs every leakage current the board aims at the node, and it must hold its potential while doing so — a guard that sags under the intercepted current re-creates the very ΔV it exists to remove. In the common case of an op amp buffering the node anyway, the buffer’s own output is a copy of the node potential at low impedance, and can drive the guard directly.

Guard both faces, and stitch: the boxing guard

A ring on the top copper guards the top surface. The bottom face has its own surface film, and the laminate between layers its own resistance, so SCDA042’s best practice extends the guard into the third dimension — first by burying the sensitive net on an inner layer, out of reach of surface contamination entirely, then by boxing it:

in addition to the traditional guarding which is just on the same layer as the net, the layers above and below also provide shielding by being at the same potential as the guard traces. This type of configuration will mimic the effects of a shielding cable in which it shields the net 360°.

The stitching vias are not decoration: without them the top pour, bottom pour and side traces are four separate conductors that merely happen to share a net name at some distant junction, and the surface between via-less edges is unguarded board. Stitched, the pieces close into the cable-shield geometry the quote describes — every face the buried net can see is guard potential.

Guarding an op amp’s input pins

The net does not end where the trace meets the package. The input pins, their pads, and the solder fillets are all part of the high-impedance node, sitting a pin-pitch away from supply pins carrying the full rail. The ring therefore wraps the input pins themselves:

On an SOIC-8 the ring enters between pins 1 and 2, wraps both inputs and their traces, and exits between pins 3 and 4 — the geometry SCDA042 shows for its multiplexers. Pitch is the constraint: the note’s advice for fine-pitch packages is to run the guard ring and traces as close to the pin as possible while still leaving space between adjacent guard traces, accepting that the ring cannot fully close. Where a full ring matters, package choice becomes a layout decision — which is the next section.

Guarding a multiplexer’s inputs

A multiplexer multiplies the problem by its channel count: every source trace is its own high-impedance net, at its own potential, with its neighbours as aggressors. SCDA042’s layout answer is one guard per channel, each driven at its own channel’s potential — a shared guard would place the channel-to-channel voltage differences across exactly the small gaps the guard created.

This is also where SCDA042 makes the package argument explicit: wide-pitch SOIC devices — its example is the MUX36S16 — leave enough room between pins for a full guard ring around each one, which is why the note calls them guarding-friendly. The selection tables back up the effort: the parts this layout work protects specify 3 pA to 100 pA of on-leakage at 25 °C, numbers that only survive contact with a real board if the guarding does its job. The note is direct about that dependency: the low leakage performance can only be achieved with proper layout and guarding implemented.

What a guard cannot fix

A guard removes the voltage difference across the board’s parasitics. It does nothing about error mechanisms that never flow across the surface — and two of them travel with the same soldering iron that built the board. SBOA590 on flux:

Residual solder flux has a high impedance that changes over time, humidity, and temperature. Solder flux residue is most problematic in applications involving high impedance circuits.

Flux residue inside the guarded region — between the input pins, under the package — is inside the ΔV ≈ 0 zone and mostly disarmed, which is one more argument for wrapping the pins rather than just the trace. But flux across the feedback network changes the gain; SBOA590’s bridge-amplifier experiment shows an uncleaned board drifting for tens of minutes as the residue absorbs humidity, and its cleaning advice is specific: follow the flux manufacturer’s process (water-soluble flux commonly comes off in a 60 °C ultrasonic bath), and for the pH-probe class of impedance, clean multiple times with different solvents. Then stop touching it:

In ultra-high impedance applications it is important to avoid directly handling the PCB as oil, moisture, and salt from skin can introduce errors.

A fingerprint is an electrolyte film. On a guarded board it lands mostly on guard copper — but across an unguarded feedback resistor it is a resistor of its own. If a precision channel that measured well on day one drifts by the week, surface chemistry belongs on the suspect list right next to the amplifier — the same discipline as any bring-up debugging: change one variable, and clean before condemning the silicon.

The checklist

Before trusting a high-impedance measurement to a layout:

1. What is the node’s source impedance, and what error does 5 nA produce across it? If the answer clears your budget with margin, stop; guards cost area and a buffer.
2. What potentials neighbour the node, on both faces and inner layers? Every volt of neighbour ΔV is a nanoamp per gigaohm aimed at the node.
3. Ring the node at its own potential — driven from a precision buffer or an existing low-impedance copy of the node, grounded only if the node itself sits at ground.
4. Wrap the pins, not just the trace, as close as the pitch allows; pick wide-pitch packages where a closed ring matters.
5. Bury the net and box it — guard above, below, beside, stitched with vias.
6. Clean the board per the flux vendor’s process, and keep fingers off the guarded area afterwards.
7. Re-check the budget at temperature. Leakage doubles every 10 °C; the 25 °C column of the datasheet is the best the part will ever look.

Sources

• TI SCDA042 — Guarding in Multiplexer Applications — the gigaohm trace-to-trace estimate, the guard principle and best practices (boxing, pitch, buffer drive), the V_ERROR equation, and the multiplexer leakage and offset-error tables.
• TI SBOA590 — Op Amp Offset Voltage and Bias Current Limitations — the V_OS and I_B error model and worked OPA205A example, the technology comparison down to femtoamp CMOS inputs, leakage over temperature, and the flux-residue and handling guidance.

Updates

• 2026-09-13 — Corrected the rate at which CMOS input bias current rises with temperature to roughly 2× per 10 °C, about 1000× between room temperature and 125 °C as SBOA590 states; the earlier “3× per decade of degrees” overstated it by orders of magnitude.
• 2026-09-13 — Fig 1 and Fig 8 redrawn to move labels off a wire and off the guard copper.