Voltage divider calculator

Output voltage of a resistive divider, the current it burns, and what each resistor dissipates. It also gives you the nearest E24 part and what that substitution actually does to the output.

Fig 1 — Unloaded divider. 250 µA flows through the chain at all times.

Solve for

Input (V)

R1 (upper) (Ω)

R2 (lower) (Ω)

Preferred series

Resistor tolerance (%)

Load resistance (0 for none) (Ω)

ADC sampling cap (0 to skip) (pF)

Output: 2.50 V
Nearest E24: 10.0 kΩ → 2.50 V
Chain current: 250 µA
P in R1 / R2: 625 µW · 625 µW
Output impedance (Thevenin): 5.00 kΩ
Worst case, ±1 % parts: 2.48 V to 2.52 V (-1.00 % / +1.00 %)

How this is calculated

Standard: Ohm's law, unloaded divider

$V_{out} = V_{in} \cdot \frac{R_2}{R_1 + R_2}$
$I = \frac{V_{in}}{R_1 + R_2}$
$P = I^2 \cdot R$: Per resistor.
$R_2 = R_1 \cdot \frac{V_{out}}{V_{in} - V_{out}}$
$R_{th} = R_1 \parallel R_2$: Output impedance.
$V_{out(load)} = V_{in} \cdot \frac{R_2 \parallel R_L}{R_1 + R_2 \parallel R_L}$
$R_1(1 \mp \text{tol}), \quad R_2(1 \pm \text{tol})$: Worst-case tolerance corners.
$t_{settle} = R_{th} \cdot C_{sample} \cdot \ln(2^{\,bits+1})$: ADC settling, to half an LSB.

Assumptions

Unloaded output. Any load in parallel with R2 pulls the output down.
A divider is a reference, not a supply — feed it into a high-impedance input.
Ideal resistors: tolerance stacks directly onto the output.
No temperature coefficient or self-heating.
For an ADC input, check the source impedance against the sampling capacitor.

What sets a divider's ratio, and its loading error

Two resistors in series across a source, output taken from the junction. With nothing connected to the output the current through both resistors is the same, so the output is just the source scaled by the ratio of the lower leg to the total. That is Ohm's law and Kirchhoff's voltage law, nothing more; there is no standard to cite because there is nothing to standardise. That divider, the current through it and the dissipation in each leg are the first three expressions under How this is calculated above.

The second mode inverts the same equation to find the lower resistor for a target output, given the upper one, which is the fourth.

The calculator then snaps R2 to the nearest E24 value (IEC 60063, closest in log distance) and recomputes the output with that part, because the number you solved for is never a number you can buy.

Voltage divider chart: common input and output pairs

The pairs a board actually needs, with a 10 kΩ upper resistor and the lower one rounded to the nearest E24 value. The output column is what that real pair gives, computed by the calculator above, and the error column is what the rounding costs before any resistor tolerance is added. Scale both resistors together for a different current; the ratio, and therefore the output, does not move.

In	Out wanted	R1 (top)	R2 (bottom)	Out, actual	Error	Current
5 V	3.3 V	10 kΩ	20 kΩ	3.333 V	+1.0 %	167 µA
5 V	2.5 V	10 kΩ	10 kΩ	2.500 V	+0.0 %	250 µA
5 V	1.8 V	10 kΩ	5.6 kΩ	1.795 V	−0.3 %	321 µA
12 V	5 V	10 kΩ	7.5 kΩ	5.143 V	+2.9 %	686 µA
12 V	3.3 V	10 kΩ	3.9 kΩ	3.367 V	+2.0 %	863 µA
12 V	2.5 V	10 kΩ	2.7 kΩ	2.551 V	+2.0 %	945 µA
24 V	12 V	10 kΩ	10 kΩ	12.000 V	+0.0 %	1.20 mA
24 V	5 V	10 kΩ	2.7 kΩ	5.102 V	+2.0 %	1.89 mA
24 V	3.3 V	10 kΩ	1.6 kΩ	3.310 V	+0.3 %	2.07 mA
48 V	12 V	10 kΩ	3.3 kΩ	11.910 V	−0.8 %	3.61 mA
48 V	5 V	10 kΩ	1.2 kΩ	5.143 V	+2.9 %	4.29 mA
48 V	3.3 V	10 kΩ	750 Ω	3.349 V	+1.5 %	4.47 mA

Worked example: monitoring a 12 V rail with a 3.3 V ADC

A 12 V rail monitored by a 3.3 V ADC. Upper resistor fixed at 27 kΩ, solve for the lower one.

R2 = 27 000 · 3.3 / (12 − 3.3)
   = 89 100 / 8.7
   = 10 241 Ω

nearest E24 = 10 kΩ

Vout (10 kΩ) = 12 · 10 000 / 37 000 = 3.243 V
I            = 12 / 37 000          = 324.3 µA
P_R1         = (324.3e-6)² · 27 000 = 2.84 mW
P_R2         = (324.3e-6)² · 10 000 = 1.05 mW

Entering 12 V, 27 kΩ, 10 kΩ in output-voltage mode gives 3.24 V, 324 µA, 2.84 mW and 1.05 mW (three significant figures). Both dissipations are far under a 0603's 100 mW rating, so power is not the constraint here; the ratio and the source impedance are.

Now add the two things the calculator deliberately leaves out.

Loading. Looking back into the output, the source impedance is R1 in parallel with R2 (Thevenin). Anything hung on the output is in parallel with R2 and pulls the ratio down. (How a fixed currentsplits between parallel resistors is the dual problem, and has its owncurrent divider calculator.)

R_th = 27k ∥ 10k = 7.30 kΩ

load 1 MΩ:   R2' = 10k ∥ 1M   = 9.90 kΩ   Vout = 12 · 9.90 / 36.90 = 3.220 V   (−0.7 %)
load 100 kΩ: R2' = 10k ∥ 100k = 9.09 kΩ   Vout = 12 · 9.09 / 36.09 = 3.023 V   (−6.8 %)

A 100 kΩ load costs almost 7 %, which is more than the ADC's whole error budget. The rule: load impedance at least 100× the Thevenin impedance for a 1 % hit, and even then it is a systematic offset you should calibrate out.

Tolerance. Two 1 % parts, worst case pulling in opposite directions:

R1 +1 %, R2 −1 %:  12 · 9 900 / (27 270 + 9 900)  = 3.196 V   (−1.45 %)
R1 −1 %, R2 +1 %:  12 · 10 100 / (26 730 + 10 100) = 3.291 V   (+1.47 %)

The ratio error is roughly 2 % × R1/(R1+R2), so it approaches the sum of both tolerances when the division ratio is large and about 1 % when the resistors are equal. Same-reel parts track better than that, but you cannot design on it.

Where the ideal divider stops being valid

Any real load. The formula is for an open output. Once the load is within a couple of decades of R1 ∥ R2, do the parallel combination yourself as above, or put a buffer between the divider and the load. A divider is a reference, not a supply; if you need current, use a regulator.
ADC inputs with a sampling capacitor. A SAR ADC's input is not a resistor, it is a switch and a capacitor (typically 5–15 pF) that must charge to within half an LSB during the acquisition window. The time constant is R_th × C_sample; for 12-bit settling you need about 9 τ. With R_th = 7.3 kΩ and 10 pF that is 0.66 µs, fine at a 2 µs acquisition, not fine at 100 ns. Most vendors publish a maximum source impedance versus sampling time table; use it, or add a 100 nF capacitor across R2 so the divider looks low-impedance at the instant of sampling. That capacitor turns the divider into a low-pass filter with f_c = 1 / (2π · R_th · C), which is usually what you wanted anyway.
Battery monitors. The chain draws Vin / (R1 + R2) continuously. 324 µA is nothing on a bench supply and is 2.8 mAh per day on a coin cell. Either go to megohm values and accept the ADC settling problem, or switch the top of the divider with a P-channel FET and only sample when it is on.
Self-heating, tempco, working voltage. Irrelevant at milliwatts. Past a quarter of rated power, thick-film tempco moves the ratio; above 75 V a 0603 exceeds its working voltage regardless of power.

Common voltage divider mistakes

Trusting the unloaded number and then feeding the output to a 10 kΩ comparator input or an op-amp with bias current in the microamps. Theop-amp error budget calculator puts that bias current through the divider's own source impedance and totals it against offset and drift.
Sizing for the ADC's DC input resistance (often quoted as ">1 MΩ") and ignoring the sampling capacitor, which is the thing that actually sets the maximum source impedance.
Picking values that give the exact ratio and then substituting the nearest E24 parts without recalculating. 10.24 kΩ became 10 kΩ above and moved the output by 1.7 %.
Adding a 1 % tolerance once instead of stacking both resistors in opposite directions. The worst case is nearly ±2 % for a high-ratio divider.
Using 100 kΩ-plus resistors on a battery monitor and then reading noise, because the high impedance node picks up everything and the ADC never settles.