Bypass capacitor placement calculator

A bypass capacitor resonates where its mounting says, not where its datasheet does: XAPP623's 10 nF is 53 MHz alone and 38 MHz once its lands and vias are added, and a 0402 land with long traces to its vias is 4 nH against 0.4 nH with two vias per side. Distance is the other limit, a phase one — the round trip to the capacitor has to be a small fraction of a quarter wave at that mounted resonance, XAPP623's λ/40, which is 30 mm for a 1 nF and metres for a 4.7 µF. Enter the capacitor, its land pattern, any trace, the vias it reaches the planes through and where it sits, and get the in-system inductance, the mounted resonance, the placement radius, and whether the distance entered is inside it.

Fig 1 — XAPP623's placement radius, one fortieth of the wavelength at the mounted resonance, against capacitance. The mounting's 3.20 nH moves the 100 nF from the thin line to the blue one: as mounted it resonates lower, its wavelength is longer, and it may sit within 487 mm of the pins. The dashed line is where it actually is.

Capacitance (nF)

Capacitor's own inductance (nH)

Land pattern (XAPP623 fig 6)

Extra trace to the via (mm)

Trace inductance (nH/cm)

Vias in series

Via height (mm)

Via diameter (mm)

Distance to the pins (mm)

Inductance: capacitor · lands · trace · vias: 900 pH · 800 pH · none · 2.40 nH
In-system inductance L_IS: 4.10 nH — 78 % of it is the board
Self-resonance (datasheet) · mounted resonance F_RIS: 16.8 MHz · 7.86 MHz
Wavelength in FR-4 at F_RIS · placement radius λ/40: 19.5 m · 487 mm
At 20.0 mm: round trip · share of a quarter wave: 261 ps · 0.4 %
One via, SLOA069 formula: 1.20 nH

A radius of 487 mm is bigger than most boards — XAPP623's 4.7 µF "can be placed anywhere on the board". For a 100 nF the distance is not the constraint; the mounting is.

The board adds 3.20 nH to the capacitor's 900 pH and moves its resonance from 16.8 MHz to 7.86 MHz. XAPP623: the mounting "typically contributes about the same amount or more inductance than the capacitor's own parasitic inductance", which is why the land pattern and the via length are worth more than the choice of part.

The 2 vias are 59 % of L_IS. A capacitor on the far side of the board pays the full stack twice; the same part on the side whose plane pair is nearest, or blind vias to an adjacent plane, cuts that to a fraction — SLOA069's 0.15 mm microvia is 0.07 nH.

How this is calculated

Standard: Xilinx XAPP623; TI SLOA069

$L_{IS} = L_{SELF} + L_{MOUNT} + L_{trace} + n_{via} L_{via}$: XAPP623: the capacitor's inductance plus the mounting's. Lands from figure 6, trace from SLOA069's per-centimetre rate, vias from its formula.
$F_{RIS} = \frac{1}{2\pi\sqrt{L_{IS} C}}$: The mounted resonant frequency, "considerably" below the datasheet self-resonance.
$L_{via} \approx 5.08\, h \left[\ln\frac{4h}{d} + 1\right]\ \text{nH}$: SLOA069, h and d in inches: 1.1 nH for 0.4 mm through 1.5 mm, 0.07 nH for a 0.15 mm microvia through 0.15 mm.
$\lambda = \frac{1/F_{RIS}}{166\ \text{ps/inch}}, \qquad R_{PLACE} = \frac{\lambda}{40}$: XAPP623 equations 3 and 4: the wavelength in FR-4 at the mounted resonance and "one tenth of a quarter wavelength".

Assumptions

The land-pattern inductances are XAPP623's figure 6 values for an 0402 with its drawn dimensions; other lands differ.
Traces add inductance at a fixed rate per centimetre; SLOA069's full formula depends weakly on width and height.
Plane spreading inductance between the capacitor and the pins is not included.
Propagation in the plane pair is 166 ps per inch, XAPP623's figure for FR-4.
λ/40 is the target XAPP623 recommends; the transition from effective to ineffective is gradual up to a quarter wave.

What sets where a bypass capacitor can go

Two things, and they are not the same. The first is the inductance the capacitor is connected through. XAPP623 draws the loop — "the path through one power plane, up through one via, through the connecting trace to the land, through the capacitor, through the other land and connecting trace, down through the other via, and into the other plane" — and puts numbers on it: "the vias, traces, and pads of a capacitor mounting contribute anywhere from 300 pH to 4 nH of inductance depending on the specific geometry", and "the capacitor mounting (lands, traces and vias) typically contributes about the same amount or more inductance than the capacitor's own parasitic inductance". Its figure 6 is the calculator's land-pattern menu: long traces to end vias 4 nH, vias hard against the lands 0.8 nH, vias to the side 0.6 nH, two vias per side 0.4 nH. SLOA069 adds the per-length rate for anything longer — "between 6 nH and 12 nH per centimeter" — and the via formula, 1.1 nH for a 0.4 mm hole through 1.5 mm of board. Add it all to the capacitor's own inductance and the part resonates where the board says, not where the datasheet does: XAPP623's 10 nF goes from 53 MHz alone to 38 MHz mounted.

The second is distance, and it is a phase question rather than an inductance one. XAPP623: "for a capacitor to be effective in providing transient current at a certain frequency … it must be within a fraction of the wavelength associated with that frequency." The disturbance travels from the pins to the capacitor at FR-4's "approximately 166 ps per inch" and the relief travels back; past a quarter wavelength "the energy transferred to the FPGA is negligible". Its target: "one tenth of a quarter wavelength is a good target. This leads to placing a capacitor within one fortieth of a wavelength of the power pins it is decoupling. The wavelength corresponds to F_RIS, the capacitor's mounted resonant frequency." Because the radius scales with √C, "capacitor placement is determined based on the effective frequency of each capacitor": the small ones close, the big ones wherever they fit.

Worked example: XAPP623's 1 nF, and the same part through the board

The note's own case: a 1 nF X7R in 0402 with 1.6 nH in the system, no extra trace and no vias counted.

mounted resonance   1 / (2π √(1.6 nH × 1 nF))          = 125.8 MHz
period              1 / 125.8 MHz                       = 7.95 ns
wavelength          7.95 ns / 166 ps per inch           = 47.9 inches (1.22 m)
placement radius    47.9 / 40                           = 1.20 inches (30 mm)   (XAPP623: "within 1.2 inches (3.0 cm)")

Now the same capacitor on the far side of a 1.5 mm board, reaching the planes through two 0.3 mm vias:

one via             5.08 × 0.059 in × (ln(4 × 0.059 / 0.0118) + 1) = 1.2 nH   (SLOA069 formula)
in-system L         1.6 + 2 × 1.2                       = 4.0 nH
mounted resonance   1 / (2π √(4.0 nH × 1 nF))          = 80 MHz
placement radius    (1 / 80 MHz) / 166 ps/in / 40      = 1.9 inches (48 mm)

The radius got looser, which is the trap: the capacitor may now sit further away, but only because it has become a worse capacitor, its useful band pushed down by 40 % by two holes. The note's larger example is the other end of the scale — a 4.7 µF at 1.56 MHz has a radius of "98 inches", so it "can be placed anywhere on the board" — and the 100 nF default, at 8 MHz once mounted, is nearer that end than the 1 nF one. For everything above a few nanofarads the distance is not the constraint. The mounting is.

Where the placement model stops being valid

The mounting numbers are one geometry. XAPP623's figure 6 values are for an 0402 land with the drawn dimensions; a different land, a wider trace or a thicker board shifts them. The via formula is SLOA069's approximation, and it says itself that "height is the predominant factor".
Plane inductance is not counted. The current still has to spread through the plane pair between capacitor and pins. XAPP623 tabulates that per square against dielectric thickness and wants V_CC "directly adjacent" to ground; with a thick spacing the planes add inductance the calculator does not see.
λ/40 is a target, not a threshold. The note calls it "a good target" and picks a tenth because "the capacitor is also effective at frequencies slightly above its resonant frequency". A capacitor at λ/30 is not useless; one at λ/4 is.
Above a few hundred megahertz the capacitor is not the answer. SPRABV2: "above approximately 250 MHz, PCB mounted capacitors are not very effective"; what works there is a power and ground plane pair "within 10 mils", whose only lead is the via from the die.
One capacitor is modelled. The anti-resonances a set of capacitors makes with each other and with the planes are thedecoupling calculator's job.

Common placement mistakes

A trace from the land to the via. XAPP623's 4 nH "BAD" pattern is exactly that, and SLOA069's verdict is "using PCB traces to make connections to decoupling capacitors simply cannot work". The via goes against the land, or in it.
Two capacitors on one pair of vias. XAPP623: "this technique should not be used under any circumstances" — the second part "only improves the PDS by a very small amount". Fewer capacitors, each with its own vias.
Putting every capacitor on the far side of the board because that is where it fits. Each pays the full stack twice. XAPP623: where the plane pair is in the top half of the stack, "it is advantageous to place capacitors on the top surface of the board, around the periphery of the device".
Judging a capacitor by its datasheet resonance. The mounted figure is what the pins see, and it is always lower.
Obsessing over millimetres for a 10 µF. Its radius is metres. Spend the layout effort on the 1 nF and 10 nF parts, whose radius is centimetres, and on every part's vias.