MOSFET power loss calculator: conduction, switching and junction temperature

What sets a MOSFET's power loss

A MOSFET used as a switch loses power in three ways. While it is on, the load current flows through its channel resistance, R_DS(on), and it dissipates I²·R_DS(on): the conduction loss. While it turns on or off, there is a short time with both a large current through it and a large voltage across it: the switching loss. And each cycle the driver has to charge and discharge its gate: the gate-drive loss, not all of which ends up in the MOSFET. TI's application note SLYT664, "MOSFET power losses and how they affect power-supply efficiency", sets these out for the two switches of a synchronous buck converter, and the calculator follows it equation by equation.

Conduction loss depends on the RMS current, not the average. For the high-side switch of a buck, the current is the inductor current for the fraction D = V_OUT/V_IN of each period, a trapezoid with the inductor's ripple ΔI on top. SLYT664's Equation 3 squares and averages that: P_CON = R_DS(on) × (V_OUT/V_IN) × (I_OUT² + I_RIPPLE²/12). The note is explicit that "neither of these is a function of switching frequency". The low-side switch carries the same current for the rest of the period, less the dead times, which is SLYT664's Equation 8.

Switching loss comes from SLYT664's Figure 5, the gate charge curve with the drain waveforms drawn above it. Turning on, the gate first charges to the threshold with nothing happening at the drain. It then takes a charge Q_GS2 to carry the gate from threshold to the Miller plateau, and during that time t1 the drain current rises from zero to the load current while the drain voltage stays at V_IN. On the plateau the gate voltage stops rising while a charge Q_GD goes into the gate-drain capacitance, and during that time t2 the drain voltage falls with the current flowing. The note writes the energy of each interval as a triangle, E_t1 = (V_DS × I_D/2) × t1 and E_t2 = (V_DS/2 × I_D) × t2, with t1 = Q_GS2/I_G and t2 = Q_GD/I_G, and doubles the sum for the two edges: P_SW = 2 × (E_t1 + E_t2) × f_SW, which is its Equation 4. Only the charge between threshold and the end of the plateau costs switching loss; the charge below threshold and above the plateau costs only gate-drive power.

The gate current I_G is where the two edges differ. On the plateau the gate sits at V_PLAT, so at turn-on the driver pushes current in with V_DRV − V_PLAT across the gate loop, and at turn-off it pulls current out with only V_PLAT. Nexperia's AN90059 gives exactly this, as I_{G_pl} = (V_drive − V_pl)/R_G(tot), with V_drive = 0 at turn-off, and adds that "turn-off is typically slower than turn-on". SLYT664's factor of 2 assumes one I_G for both. The calculator uses the two gate currents separately, each through its own side of the driver (R_GHIsourcing, R_GLO sinking) plus the external and internal gate resistances. It also switches the valley of the inductor current, I_OUT − ΔI/2, at turn-on and the peak, I_OUT + ΔI/2, at turn-off, a refinement that is not in SLYT664. With a symmetric drive both refinements cancel and the result is Equation 4 exactly; the unit tests check that.

Gate-drive loss is SLYT664's Equation 5, P_GATE = Q_G(TOT) × V_G × f_SW, the energy to charge the gate to V_DRV and discharge it again, every period. Equation 6 splits it between the resistances the charge flows through, the driver's, the external gate resistor's and the MOSFET's own internal gate resistance, in proportion to their values, and the note says plainly that "gate-drive losses do not all occur on the MOSFET". Only the share in the internal resistance heats the junction, so that is what the calculator adds to the MOSFET's dissipation. It also shows SLYT664's own total, which counts all of P_GATEagainst the FET as its Figures 8 and 11 do.

The low-side switch has no switching loss in SLYT664's account: "The body diode conducts and the voltage across the FET is the diode voltage, which is zero. The body diode ensures zero-voltage switching." In its place is the body diode's own loss during the two dead times, Equation 10, P_BD ≈ V_F × I_OUT × (t_DLYUpLo + t_DLYLoUp) × f_SW. The total loss becomes a junction temperature through T_J = T_A + R_θJA × P, the equation TI's SPRA953 gives as the one "usually assumed to be valid", and warns about; more on that below.

MOSFET losses against switching frequency

The high-side switch of the default design, a 12 V to 1.1 V, 20 A buck, at five switching frequencies. Conduction loss does not move; switching and gate loss rise in proportion to f_SW. The junction temperature uses the datasheet's 50 °C/W from 50 °C ambient, and the R_DS(on) factor is held at 1.5 throughout.

This is the shape of SLYT664's Figure 8, where a flat conduction line is crossed by a rising switching curve. Here the crossover is at 103 kHz: above it the high side's gate charge matters more than its R_DS(on). At a duty cycle of 9 % the high side conducts only briefly, but it switches the whole 12 V at every edge, which is why a 12 V to 1 V converter spends most of its high-side loss in switching even at moderate frequency. From 200 kHz to 2 MHz the loss in the package goes from 694 mW to 4.85 W. The note's advice follows directly: "a higher switching frequency and higher input voltage require a lower QG (gate charge) to cut down the switching losses in the switch MOSFET (Q1)."

High side and low side against load current

The same design at 600 kHz across load current, the ripple held at 6 A. The high side's switching loss grows in proportion to the current; both conduction losses grow with its square, plus the ripple's share.

At 5 A the high side dissipates 454 mW and the low side 232 mW; at 20 A, 1.62 W and 985 mW. The two parts were chosen for their jobs, and it shows in how their losses are made up. The high side, a small CSD17577Q5A with 27 nC of gate charge at 10 V, spends its loss on switching. The low side, a CSD17573Q5B with a quarter of the R_DS(on) and four times the gate charge, carries the current for 88 % of the period without switching loss, so its I²R stays small and its gate charge and body diode take a large share. SLYT664 says the same: "For a rectifier MOSFET (Q2), low RDS(on) is most important, but don't ignore the gate power."

Worked example: CSD17577Q5A and CSD17573Q5B in a 12 V to 1.1 V, 20 A buck

SLYT664 has no numerical example, so this one is built from documents that do. The operating point is the test circuit of TI's SLYT465, "a 1.1-V/20-A buck converter" on the TPS40304 "600-kHz buck controller", with a 12 V input. The high side is a TI CSD17577Q5A, which its datasheet describes as having "Low Qg and Qgd"; the low side a TI CSD17573Q5B, "Ultra-Low RDS(on)". Both datasheets tabulate R_DS(on) and Q_g at V_GS = 4.5 V and 10 V; the example drives both at 10 V, an assumption, because the controller's drive voltage is not among the sources here. The 4.5 V case follows below.

From the CSD17577Q5A's table (page 3): R_DS(on) 4.2 mΩ maximum at 10 V (3.5 mΩ typical), Q_g 27 nC at 10 V, Q_gs 5.1 nC, Q_g(th) 2.5 nC, Q_gd 2.8 nC, all typical at V_DS = 15 V and I_D = 18 A, a series gate resistance of 1.4 Ω and a threshold of 1.4 V. The maximum R_DS(on) is used because the conduction loss should be the guaranteed one; the charges are typical because Q_gs, Q_g(th) and Q_gd have no maximum in the table. TI defines Q_gs as the charge to the start of the plateau and Q_g(th) as the charge at V_th, so Q_GS2= 5.1 − 2.5 = 2.6 nC; on the datasheet's Figure 4 the curve does cross about 1.4 V at 2.5 nC. The plateau, about 2.7 V, is read off that figure: the curve is not flat but bends between about 5 nC and 8 nC. The normalised R_DS(on) of Figure 8 is about 1.5 at 130 °C for V_GS = 10 V, read off the curve at the junction temperature the example reaches. R_θJA is 50 °C/W maximum, for a "Device mounted on FR4 material with 1-inch2 (6.45-cm2), 2-oz. (0.071-mm thick) Cu", and 140 °C/W on a minimum pad.

The rest: 6 A of ripple, 30 % of 20 A, the top of SNVA559's "less than 20% to 30%"; a driver of 5 Ω each way, the figure SLUP170's Appendix A uses, "RLO=RHI=5Ω the output resistances of the gate driver circuit"; no external gate resistor, as in SLYT465's baseline; and 50 °C ambient, the ambient of SNVA419's thermal example. The 20 ns dead times are an assumption; none of the sources gives one.

duty      D = 1.1 V / 12 V                             = 0.0917
RMS       I_RMS² = D × (20² + 6²/12)                   = 36.94 A²
P_CON     4.2 mΩ × 1.5 × 36.94 A²                      = 233 mW
Q_GS2     Q_gs − Q_g(th) = 5.1 nC − 2.5 nC             = 2.6 nC
I_G on    (10 V − 2.7 V) / (5 + 0 + 1.4) Ω             = 1.14 A
I_G off   2.7 V / (5 + 0 + 1.4) Ω                      = 422 mA
t1 on     2.6 nC / 1.14 A                              = 2.28 ns
t2 on     2.8 nC / 1.14 A                              = 2.45 ns
E_on      12 V × 17.0 A / 2 × (t1 + t2)                = 483 nJ
t1 + t2   off: 5.4 nC / 422 mA                         = 12.8 ns
E_off     12 V × 23.0 A / 2 × (t1 + t2)                = 1.77 µJ
P_SW      (E_on + E_off) × 600 kHz                     = 1.35 W
P_G       27 nC × 10 V × 600 kHz                       = 162 mW
in R_G,I  P_G × 1.4 Ω / 6.4 Ω                          = 35.4 mW
P_D       P_CON + P_SW + P_G in R_G,I                  = 1.62 W
T_J       50 °C + 50 °C/W × 1.62 W                     = 131 °C

Switching is 5.8 times the conduction loss, and the turn-off edge alone accounts for 79 % of it: it switches 23.0 A rather than 17.0 A and has 422 mA of gate current rather than 1.14 A, so it takes 12.8 ns against 4.73 ns. Equation 4 with one gate current for both edges would give 682 mW using the turn-on current and 1.84 W using the turn-off one; the 1.35 W between them is what separating the edges buys. Of the 162 mW of gate-drive power, only 35.4 mW is dissipated in the FET; SLYT664's own per-FET total, counting all of it, is 1.74 W. The junction, at 131 °C, is where the 1.5 factor was read, so the estimate is self-consistent.

The low side, from the CSD17573Q5B's table (page 3): R_DS(on)1.00 mΩ maximum at 10 V (0.84 mΩ typical), a series gate resistance of 0.9 Ω, and a body diode V_SD of 0.8 V typical at 35 A, used as it stands although the diode carries 20 A here. The table gives Q_g only at 4.5 V, 49 nC; at 10 V the datasheet's Figure 4 reads about 111 nC. Its Figure 8 gives a factor of about 1.4 at 100 °C. R_θJA is again 50 °C/W.

share     1 − D − (20 + 20) ns × 600 kHz               = 0.8843
P_CON     1.0 mΩ × 1.4 × 0.8843 × 403 A²               = 499 mW
P_BD      0.8 V × 20 A × 40 ns × 600 kHz               = 384 mW
P_G       111 nC × 10 V × 600 kHz                      = 666 mW
in R_G,I  P_G × 0.9 Ω / 5.9 Ω                          = 102 mW
P_D       P_CON + P_BD + P_G in R_G,I                  = 985 mW
T_J       50 °C + 50 °C/W × 985 mW                     = 99 °C

Of the low side's 985 mW, conduction is 499 mW, and without the temperature factor it would be 356 mW, with the junction at 92 °C instead of 99 °C. The high side's conduction loss is 155 mW cold and 233 mW hot, a difference that matters less because switching dominates it.

Driven at 4.5 V instead, the high side has 5.8 mΩ maximum and 13 nC from the same table, and only 1.8 V of headroom over its plateau to drive turn-on, against 7.3 V at 10 V. With the same temperature factor, its switching loss rises to 2.23 W, its total to 2.56 W, and its junction to 178 °C, past the 150 °C top of its operating range (where the factor would in fact be higher still). The lower gate charge does not make up for the lower gate current.

Checks against published numbers

The pieces of the model that the sources work numerically are reproduced exactly. Nexperia AN90059 works the plateau gate current for its BUK7S1R0-40H with a 10 V drive, a total gate resistance of 10 Ω and a plateau "around 4.2 V": I_{G_pl(on)} = (10 − 4.2)/10 = 0.58 A and I_{G_pl(off)} = (0 − 4.2)/10 = −0.42 A. The calculator gives 580 mA and 420 mA. The same note gives the gate-drive power "98nC*10V*100kHz = 98mW", which is SLYT664's Equation 5; the calculator gives 98.0 mW. Infineon's gate-drive note works "27 nC x 14 V x 100 kH = 38 mW" for a 100 kHz switcher; the calculator gives 37.8 mW.

AN90059 also derives the plateau times: R_gQ_gd/(V_G− V_GS(pl)) at turn-on (its Formula 14) and R_gQ_gd/V_GS(pl) at turn-off (Formula 17), which are the calculator's t2 for each edge. Its Table 1 lists the values those formulas give for a 10 V drive and a 47 Ω external resistor: 140 ns and 194 ns. The note does not print the Q_gdand internal resistance it used, but their ratio does not depend on them, and 194/140 implies a plateau of 4.19 V, consistent with its "around 4.2 V". The same table has the simulation beside the calculation, 155 ns against 140 ns at turn-on and 209 ns against 194 ns at turn-off: the formulas come out 7 % to 10 % short of the simulated plateau.

A MOSFET as a static switch: I²R and the gate drive

Many MOSFETs never switch at speed: a load switch, a reverse-polarity FET, a high-side power switch that stays on for minutes. Then the only loss is conduction, P = I² × R_DS(on), and the calculator's static mode computes that and the junction temperature. The trap is the gate voltage. AN90059 uses the BUK6D16-30E, with R_DSon of "13.4 mΩ @ VGS = 10 V or 17 mΩ @ VGS = 4.5 V", and marks its curve at 24 mΩ for a 3.3 V drive, where the part "still has a high drain-source resistance at 3.3 V VGS". Carrying 3 A, that is 216 mW at 3.3 V against 121 mW at 10 V. At a hot junction the 10 V figure rises too: with the factor of about 1.7 read from the same figure, 205 mW. With an assumed 60 °C/W from 50 °C, those three become 63 °C, 57 °C and 62 °C at the junction.

Where the loss model stops being valid

Linear edges and a constant gate current. The model draws the current and voltage transitions as straight lines and holds the gate current at its plateau value throughout. Balogh's gate-drive note, TI SLUA618, calls this "a crude estimate" and explains why a better one is out of reach: "calculating the exact switching losses is almost impossible. The reason is the effect of the parasitic inductive components significantly alter the current and voltage waveforms". It also refines t1 by driving the gate from the average of threshold and plateau rather than the plateau alone, which shortens turn-on a little; this calculator keeps SLYT664's single gate current per edge.

Output capacitance. The model's switching energy is the overlap of the channel's current and voltage. The MOSFET's output capacitance C_OSS, charged to V_IN while it is off, is discharged through its own channel at every turn-on, and that energy is not in SLYT664's equations or in this calculator. This is physics, not a figure from the sources here; read E_OSS or Q_OSSoff the datasheet if it lists one and add it at high input voltage.

Reverse recovery of the low-side body diode. SLYT664's Figure 9 shows the body diode conducting through both dead times. When the high side then turns on, that diode has to recover before the switch node can rise (this and the rest of the paragraph's mechanism is physics, not a figure from the sources here), and its recovery charge flows through the high side while it has V_IN across it. That loss lands in the high side and is not modelled. AN90059 lists reducing "reverse recovery current (since it is a function of dI/dt)" among the advantages of slower switching.

Ringing. TI's SLYT465 describes the energy in the parasitic inductances that "appears as an LC ringing waveform on the switch node" at each high-side turn-on, 23.4 V peak on a 12 V input in its test circuit. Damping it costs efficiency: at 12 V, full-load efficiency went from 87.2 % to 85.2 % with a 6.8 Ω high-side gate resistor, which the note calls "the least efficient of the three choices" because it slows both edges. In this model the same 6.8 Ω raises the default high side's switching loss from 1.35 W to 2.78 W.

Discontinuous mode and light load. The equations assume the inductor current never reaches zero. When the ripple exceeds twice the load, the calculator stops; the losses at light load depend on the controller's light-load mode.

R_θJA. TI's SPRA953 is blunt about the thermal step: R_θJA is measured on a JEDEC test board, "in still-air JEDEC-defined RθJA measurements, almost 70%–95% of the power generated by the chip is dissipated from the test board", and "because a system board rarely approximates the test coupon used to determine RθJA, application of RθJA using Equation 1 results in extremely erroneous values." TI's SNVA419 puts its proper use as a way "to compare different packages, and use it along with the IC power dissipation for a sanity check in your design". The junction temperature here is that sanity check. For a MOSFET on a heat sink, use R_θJC and the heat sink chain instead; the calculator also reports the most the package can dissipate at the R_θJA entered, which is the form TI's SLVA079 uses for a linear regulator.

Common MOSFET power loss mistakes

• Using R_DS(on) at 25 °C. The table value is at a cool junction; the operating one is hotter and so is the resistance. In the example the low side's conduction loss is 356 mW at the table value and 499 mWwith the factor of 1.4 its Figure 8 gives at 100 °C.
• Reading R_DS(on) or Q_G at a different V_GSfrom the one the driver applies. The CSD17577Q5A's 13 nC at 4.5 V, used for a 10 V drive, gives 78.0 mW of gate loss instead of the 162 mWits 27 nC at 10 V gives at 600 kHz; its R_DS(on) differs by the same kind of step, 5.8 mΩ against 4.2 mΩ maximum.
• Using Q_GS for Q_GS2. Only the charge from threshold to plateau is spent with current flowing; the part below threshold is not switching loss. Using the CSD17577Q5A's whole 5.1 nC Q_gs instead of its 2.6 nC Q_GS2 would put the example's switching loss at 1.97 W instead of 1.35 W.
• Forgetting the gate driver. With a large, low-R_DS(on) part P_G can exceed the conduction loss: the example's low side takes 666 mW of gate drive against 499 mW of conduction. Most of it heats the driver or controller, which then needs its own thermal check. SLYT664: "Larger MOSFETs with lower RDS(on) provide lower conduction losses at the cost of higher gate capacitances, which results in higher gate-drive losses."
• Assuming turn-off is as fast as turn-on. With V_DRV = 10 V and a 2.7 V plateau the turn-on current is 2.70 times the turn-off current through equal driver resistances. A driver with a strong sink, or a separate turn-off path, is worth more than a strong source.
• Sizing at one input voltage. The high side's switching loss is worst at the highest V_IN, its conduction loss at the lowest.
• Trusting R_θJA as a board property. It is a property of the JEDEC test board. Measure the case, or use the heat sink chain.

Further reading

• TI SLYT664, MOSFET power losses and how they affect power-supply efficiency — Equations 3 to 10: conduction, switching, gate-drive and body-diode loss, and Figure 5, the gate charge curve the switching loss is built on.
• TI CSD17577Q5A 30-V N-channel NexFET datasheet — the example's high side: page 3's table, the gate charge curve (Figure 4) and normalised R_DS(on)against temperature (Figure 8).
• TI CSD17573Q5B 30-V N-channel NexFET datasheet — the example's low side: its R_DS(on), gate charge, body diode and thermal resistance.
• Nexperia AN90059, Power MOSFET gate driver fundamentals — the plateau gate current at turn-on and turn-off, the switching times of each edge, and R_DSon against V_GS at two temperatures.
• TI SLUA618, Fundamentals of MOSFET and IGBT Gate Driver Circuits — Balogh's turn-on and turn-off intervals, the gate-drive loss and where it is dissipated.
• TI SLYT465, Controlling switch-node ringing in synchronous buck converters — the test circuit behind the example, and what damping the ringing costs.
• TI SPRA953, Semiconductor and IC Package Thermal Metrics — what R_θJA measures and why it misleads on your own board.
• Gate resistor calculator — the gate resistor from the dv/dt wanted, and the dv/dt the low side survives.
• Heat sink calculator — the junction temperature through R_θJC and a sink instead of R_θJA.
• Buck inductor calculator — the ripple current ΔI this calculator takes as an input.
• Buck converter output ripple calculator— what the same ripple current does at the output capacitor.
• Bootstrap capacitor calculator— the supply that charges the high side's Q_G every cycle.