PLL loop filter calculator: second- and third-order passive filters

What a PLL loop filter does

A charge-pump PLL compares the divided-down VCO output with the reference at the phase detector, and the charge pump turns the phase error into pulses of current. The loop filter turns that current into the tuning voltage the VCO needs. Dean Banerjee's PLL Performance, Simulation, and Design, published by Texas Instruments as SNAA106C, defines it by that job: "The loop filter impedance is defined as the output voltage at the VCO divided by current injected at the PLL charge pump" (p. 302). Its impedance, multiplied by the charge-pump gain and the VCO gain and divided by N and by s, is the open-loop gain of the whole PLL (Eq 33.8), and every property of the loop — lock time, phase noise, reference spurs, stability — follows from that function.

The design problem is the reverse. You choose a loop bandwidth and a phase margin, and the calculator finds the capacitors and resistors that give them. Banerjee is explicit that the filter is tied to one operating point: "The loop filter is designed for a fixed value of N, KPD, and KVCO", and it is their combination that matters, the loop gain constant K = KPD·KVCO/N (p. 299, Eq 33.1). Change the charge-pump current, the VCO or the divide ratio, and the components have to be recalculated.

The second-order passive filter is C1 from the charge-pump node to ground, in parallel with C2 in series with R2. The book calls it "the most rudimentary loop filter", one that "allows one to explicitly solve for the component values in closed form. It has the smallest resistor thermal noise and largest capacitor next to the VCO to minimize the impact of VCO input capacitance" (p. 339). The third-order filter adds R3 in series and C3 to ground at the VCO pin, an extra pole that is "useful in filtering spurs or noise caused by the PLL that is at an offset frequency of ten times the loop bandwidth or greater" (p. 344).

The units: KPD without 2π, KVCO in Hz/V

The equations only give the right components in the units they were written for. The charge-pump gain is strictly the current per radian of phase error, KPD/2π. Banerjee drops the 2π: "it is typically left out because most calculations involve multiplying it by the VCO gain, which contains a factor of 2π to convert it from MHz/volt to MRad/volt. Knowing that these will cancel, this book will use the practical definition of disregarding this factor" (p. 34). So KPD is the charge-pump current as the datasheet gives it, 1 mA for a 1 mA pump, and KVCO "is expressed in MHz/V" (p. 45), the datasheet figure again. The calculator takes both that way. Entering one of them with the 2π applied and the other without it is the error the next-to-last section works through.

The loop filter design equations

The method is the one Banerjee credits to William Keese's Application Note 1001 (p. 302). Two conditions fix the time constants: the phase of the open-loop gain at the loop bandwidth must give the phase margin asked for, and the gamma optimisation factor γ = ωc²·T2·(T1 + T3) (Eq 33.5) sets where the phase peaks. With γ = 1 the peak sits exactly at the loop bandwidth, which "is a good approximation to minimizing the lock time, but not the exact constraint" (p. 314); Banerjee's simulations then tabulate the γ that is.

For the second-order filter, substituting T2 = γ/(ωc²·T1) into the phase condition and taking the tangent of both sides gives T1 in closed form (Eq 38.7). The total capacitance A0 = C1 + C2 comes from setting the open-loop gain to one at the loop bandwidth (Eq 38.8), and the components follow: C1 = A0·T1/T2, C2 = A0 − C1, R2 = T2/C2.

For the third order there is no closed form. With the pole ratio T31 = T3/T1 chosen, the phase condition (Eq 39.8) has T1 as its only unknown, "and it can be found by numerical methods" (p. 345). Its right-hand side falls steadily as T1 grows, so the calculator solves it by bisection. Four equations then relate five components to A0, A1 and A2, and Banerjee fixes the fifth by choice: "a very good choice would be to maximize the value of C3 in order to minimize the impact of the VCO input capacitance" (p. 346). Setting dC3/dC1 = 0 gives C1 (Eq 39.21), and the appendix proves that with that C1 every part is positive as long as T2 > T1 + T3 and T31 < 100 % (pp. 348–349). The first condition is automatic here: any positive phase margin in Eq 39.7 already implies it.

The calculator does not stop at the components. It rebuilds the open-loop gain from the network itself — C1 ∥ (R2 + C2) ∥ (R3 + C3), with the VCO taking its voltage across C3 — finds the frequency where the gain crosses 0 dB, and reads the phase margin there. That is the check that the parts do what was asked, and it is what makes rounding to E-series values honest: the figure and the last rows of the result show the loop the rounded parts give, not the one that was designed.

A handful of equations are printed with errors, each confirmed against the page, and the calculator does not use them as printed. Eq 38.5 and Eq 33.9 put "180 +" in front of the arctangents; taken literally, the chapter 38 example would have a phase margin of 229.2°. The margin is the arctangent difference alone, as Eq 39.7 writes it. Eq 38.11 carries a second "= KPD·KVCO/(N·ωc²)" that is not R2. In the chapter 38 appendix, Eq 38.18 drops the squares on T1 and T2, which gives 1.043 nF instead of the printed 1.052 nF, and Eq 38.19 inverts C1 to A0·T2/T1, which would give 7.61 nF — more than the total capacitance. Eq 38.9 is what reproduces the printed 0.145 nF. In chapter 39, Eq 39.1 has a stray A0 in the numerator and Eq 39.12 has ωc where Eqs 39.6 and 39.38 have ωc². Eq 12.9 defines γ as T2/(ωc²·A0), which is not dimensionless; Eq 33.5 is used. The results table on p. 351 labels T3 a "Loop Filter Zero"; it is the second pole.

PLL loop filter components for common bandwidths

Second order, with the chapter 38 example's loop: KPD = 1 mA, KVCO = 60 MHz/V, N = 39200, fPD = 50 kHz, φ = 49.2°, γ = 1.024. Only the loop bandwidth changes down the table.

Third order, with the chapter 39 example's loop: KPD = 4 mA, KVCO = 30 MHz/V, N = 23200, fPD = 60 kHz, φ = 47.1°, γ = 1.136, T31 = 0.6.

The pattern in both tables is the scaling the equations imply: every time constant goes as 1/BW and A0 as 1/BW², so doubling the loop bandwidth quarters every capacitor and doubles every resistor. Going the other way is what limits narrow loops. The book notes that the minimum bandwidth "is limited by the loop filter capacitors becoming unrealistically large" (p. 305). The same scaling holds for K: double the charge-pump current and every capacitor doubles and every resistor halves, with the loop bandwidth unchanged. The last rows of each table are past fPD/10; see the section on the continuous-time model before using them.

Worked example: the chapter 38 second-order filter

Appendix A of chapter 38 (pp. 342–343) designs a filter for BW = 10 kHz, φ = 49.2°, γ = 1.024, KPD = 1 mA, KVCO = 60 MHz/V, fVCO = 1960 MHz and fPD = 50 kHz. These are the calculator's defaults.

divider   N = 1960 MHz / 50 kHz                        = 39200
          ωc = 2π × 10 kHz                             = 62831.9 rad/s
pole      tan 49.2° = 1.1585, (1 + γ) = 2.024
          T1 = [√((1+γ)²tan²φ + 4γ) − (1+γ)tan φ]/(2ωc) = 5.9892 × 10^−6 s
zero      T2 = γ/(ωc²·T1)                              = 4.3308 × 10^−5 s
total     A0 = KPD·KVCO/(N·ωc²)·√((1+ωc²T2²)/(1+ωc²T1²)) = 1.052 nF
parts     C1 = A0·T1/T2                                = 145.5 pF
          C2 = A0 − C1                                 = 906.5 pF
          R2 = T2/C2                                   = 47.776 kΩ
check     crossover of those parts                     = 10 kHz
          phase margin there                           = 49.200°

The book prints N = 39200, ωc = 6.283 × 10⁴ rad/s, T1 = 5.989 × 10⁻⁶ s, T2 = 4.331 × 10⁻⁵ s, A0 = 1.052 nF, C1 = 0.145 nF, C2 = 0.906 nF and R2 = 47.776 kΩ. Every one agrees with the calculation to the digits printed, and the page's tests hold it to them. Reading the loop back from those three parts gives a crossover of 10 kHz and a phase margin of 49.200°: the design targets, recovered from the components alone. The loop gain is 31.6 dB a decade below the crossover and −31.8 dB a decade above.

The φ and γ pair is not arbitrary. It is the T31 = 0 row of the book's Table 36.5 (p. 319), the choice that minimises an index of lock time and spur gain together. The fastest-lock row of Table 36.4 for the same filter is 50.8° and γ = 1.006.

Worked example: the chapter 39 third-order filter

Appendix A of chapter 39 (pp. 350–352) takes BW = 2 kHz, φ = 47.1°, γ = 1.136, KPD = 4 mA, KVCO = 30 MHz/V, fVCO = 1392 MHz, fPD = 60 kHz and T31 = 0.6, the T31 = 60 % row of Table 36.4. Load it in the calculator.

divider   N = 1392 MHz / 60 kHz                        = 23200
          ωc = 2π × 2 kHz                              = 12566.4 rad/s
poles     T1: root of Eq 39.8, by bisection            = 2.0362 × 10^−5 s
          T3 = 0.6 × T1                                = 1.2217 × 10^−5 s
zero      T2 = γ/(ωc²(T1 + T3))                        = 2.2081 × 10^−4 s
coeffs    A0 (Eq 39.13)                                = 92.5088 nF
          A1 = A0(T1 + T3)                             = 3.0139 × 10^−3 nF·s
          A2 = A0·T1·T3                                = 2.3014 × 10^−8 nF·s²
parts     C1 (Eq 39.21)                                = 6.5913 nF
          C3 (Eq 39.20)                                = 466.8 pF
          C2 = A0 − C1 − C3                            = 85.4507 nF
          R2 = T2/C2                                   = 2.5840 kΩ
          R3 = A2/(C1·C3·T2)                           = 33.8731 kΩ
check     crossover · phase margin                     = 2 kHz · 47.100°

The book's T1 is 2.0333 × 10⁻⁵ s, and it is not quite the root of its own equation: put back into Eq 39.36 it gives a phase margin of 47.158°, not 47.1°. The exact root is 2.0362 × 10⁻⁵ s, 0.14 % higher, so the components the book prints differ slightly from the exact solution. Fed the book's own T1, the component equations reproduce every printed value to within 0.0044 %, which is the rounding of that five-figure T1; the exact solve is within 0.17 % of every printed value.

The book also offers a closed-form shortcut, T1 ≈ (sec φ − tan φ)/(ωc(1 + T31)) (Eq 39.10), from the approximation tan x ≈ x ≈ tan⁻¹x. For this example it gives 1.9541 × 10⁻⁵ s, −4.0 % from the root. The calculator solves Eq 39.8 instead, so the phase margin read back from the parts is 47.100° exactly. C3 comes out at 467 pF, so by the book's rule (p. 347) the VCO's input capacitance should be no more than 117 pF.

Choosing the loop bandwidth, phase margin and gamma

Loop bandwidth. "The loop bandwidth (BW) is the most critical design parameter and has a profound impact on spurs, phase noise, and lock time" (p. 301). "Wider loop bandwidths give better lock times, but spurs that are not crosstalk dominated will be increased", and for jitter the book's starting point is the offset "where the PLL and VCO phase noise cross". At the top end: "The maximum loop bandwidth is typically limited to one-tenth of the phase detector frequency. It can also be limited by the VCO input capacitance or by loop filter component values being forced."

Phase margin. "Typically it is chosen between 30 and 80 degrees. Simulations suggest that 48 degrees is close to optimal for lock time, but higher phase margins up to 80 degree are preferable for a flatter response and also higher tolerance to variations in VCO gain" (p. 301). Lower margins "give sharper cut-off for better spur attenuation" at the cost of peaking; "for higher order filters, a low phase margin less than 20 degrees often results in instability" (p. 313). The table shows what the choice does to the chapter 38 loop at 10 kHz, with γ from the book's Table 36.3 (p. 316) for each margin.

Higher margins spread the zero and the pole apart (the T2/T1 column) and shrink C1, which is why, above about 80°, "component values in the filter start becoming too small or negative" (p. 313). The γ values come from simulations of one particular loop (Table 36.2: 5 mA, 20 MHz/V, fPD = 200 kHz, N = 4500) and the book notes they "may vary slightly if the frequency jump or frequency tolerance for lock time is changed" (p. 318); γ = 1 is the neutral starting point.

Pole ratio T31. A bigger T31 moves the third pole closer to the first and attenuates more far from the carrier, and at 100 % a passive filter needs zero capacitors and infinite resistors. Eq 37.5 gives the attenuation relative to T31 = 100 %: the book's figure is that "a pole ratio of 51% gets one within 1 dB of the maximum achievable benefit and a pole ratio of 62% gets one within 0.5 dB" (p. 327); the equation gives −0.97 dB and −0.49 dB. The 68 % suggested on p. 301 gives −0.32 dB. The cost lands on C3 and R3, with φ and γ from Table 36.4 for each T31:

Banerjee's advice for choosing it is to go "as high as realistically possible for the best lock time and spur performance, while keeping the capacitor size next to the VCO large enough to not be significantly impacted by the VCO input capacitance and the series resistor to the VCO not too large so that it does not contribute too much thermal noise" (p. 319). Whether a third pole helps at all depends on the offset: the book's rule of thumb is that it "adds value in filtering off noise/spurs that is at least ten times the loop bandwidth" (p. 330).

Where the continuous-time model stops being valid

Every equation here treats the charge pump as a continuous current. In Banerjee's words, "the phase/frequency detector technically puts out a pulse width modulated signal and not a continuous current". He names the approximation and gives its limit (pp. 39–40): it "is a valid provided that the loop bandwidth is no more than about one-tenth of the phase detector frequency". Beyond that: "In practice, one will start to see the loop go unstable when the loop bandwidth reaches about one-third of the phase detector frequency and would probably never want to exceed one-fifth the phase detector frequency to avoid any issues. Between one-tenth and one-fifth, the PLL will probably still lock, but the performance may be degraded." At the other extreme, "If the loop bandwidth is less than about 1/100th of the phase detector frequency, then the lock time could be degraded due to cycle slipping."

The chapter 38 example itself sits at the edge: 10 kHz with a 50 kHz phase detector is fPD/5, twice the one-tenth limit, and the calculator flags it. The equations still give the book's components; what the book's own limit says is that a real loop built from them will not behave exactly like the continuous-time model predicts. The figure marks fPD/10 and fPD/3 on the frequency axis whenever they fall inside it, so you can see where your crossover sits against them.

Rounding is the other place the model and the board part company. The chapter 38 parts rounded to E24 — 150 pF, 910 pF and 47.0 kΩ — cross over at 9.842 kHz with 48.77° of margin; the chapter 39 parts rounded to E12 cross at 2.06 kHz with 46.40°. Both are small moves, and both are far smaller than the spread of a real VCO gain: the chapter 38 loop with KVCO 40 % high crosses at 13.1 kHz (48.1°), and 40 % low at 6.66 kHz (47.0°). The book's ±40 % example (p. 310) is why it recommends designing a tunable PLL for the geometric mean of its loop gain (p. 299).

Common loop filter mistakes

• Applying the 2π to KPD. Entering the chapter 38 charge pump as 1 mA/2π = 159 µA with KVCO still in MHz/V designs every capacitor 6.28 times too small. Built and run with the real 1 mA, that filter crosses over at 37 kHz with 30.0° of margin instead of 10 kHz and 49.2°. The opposite slip — the right parts, but a loop whose gain really is 2π lower — crosses at 2.69 kHz with 30.4°. Use both gains as the datasheets give them, or apply 2π to both.
• Forgetting N. The loop gain is divided by the feedback divider. Leave N out of the chapter 38 design (N = 1) and the total capacitance comes out at 41.2 µF, 39200 times the right value.
• Swapping C1 and C2. The book lists it among the common assembly mistakes: "to accidentally swap C1 and C2, which leads to severe peaking" (p. 464). With the chapter 38 values swapped, the loop crosses at 6.1 kHz with only 2.0° of phase margin.
• Ignoring the VCO input capacitance. It sits in parallel with C3 (with C1 in a second-order filter), and "can cause peaking or instability if unaccounted for" (p. 464). Hence the rule that C3 "should be at least four times the VCO input capacitance" (p. 347); if it cannot be, "try decreasing the value of T31 so that C3 will become larger and R3 will become smaller". For the chapter 39 filter, a VCO input of C3/4 = 117 pF moves the loop to 1.98 kHz and 44.4°; one equal to C3 moves it to 1.9 kHz and 36.9° (derived: the capacitance added to C3 in the calculation above).
• Transcribing the appendix equations. Eq 38.18 and Eq 38.19 as printed give an A0 0.9 % low and a C1 larger than the whole filter; the equations in the body of chapter 38 are the ones to use. See the list of misprints above.
• Designing past fPD/10 and trusting the result. The components come out whatever the bandwidth, but the loop they model stops existing: the continuous-time approximation ends near fPD/10 and the loop goes unstable near fPD/3.
• Designing for one end of the tuning range. N and often KVCO change across the band. Banerjee designs for the geometric mean of the loop gain, and past about ±15 % variation suggests compensating with the charge-pump current if it is programmable (p. 299).

Further reading

• Dean Banerjee, PLL Performance, Simulation, and Design, 5th ed. (Texas Instruments SNAA106C, 2017) — the unit conventions (pp. 34, 45), the continuous-time approximation (pp. 39–40), loop filter design concepts (ch. 33), choosing bandwidth, phase margin and γ (ch. 34–36), filter order and pole ratio (ch. 37), and the second- and third-order passive filters with their worked examples (ch. 38–39).
• Active filter calculator — second-order Sallen-Key and multiple-feedback low-pass stages from a corner frequency: op-amp filters, where this page's are passive.
• RC filter calculator — the single pole that R3 and C3 add, on its own.
• LC resonance calculator — the tank frequency behind an LC VCO's tuning range.
• Crystal ppm budget calculator — tolerance, stability and aging of the reference crystal. A locked PLL output carries the same error in ppm, which at N times the frequency is N times as many hertz.