Op amp capacitive load and isolation resistor calculator

A capacitor on an op amp's output makes a pole with the amplifier's open-loop output impedance R_O; below the gain bandwidth it steals the phase margin and the output rings or oscillates. A small resistor in series with the capacitor adds a zero that cancels it, and TI's SBOA418 gives the smallest value that works: from R_O, the load and the gain bandwidth alone, 100 Ω and 1 MHz on 10 nF wants 49 Ω, and an OPA392 on 10 µF wants 380 mΩ. Enter the datasheet numbers and the load to get the pole, the margin without the resistor, the optimal R_ISO rounded up in E24, and the margin, overshoot, bandwidth and DC drop it leaves.

Fig 1 — Loop gain against frequency. The load capacitance against R_O adds a pole at 159 kHz, so the loop reaches 0 dB falling at 40 dB/decade with 23° of phase margin. 51.0 Ω in series with the load adds a zero at 312 kHz and moves the pole to 105 kHz; the slope is back to 20 dB/decade at the crossing and the margin is 67°. Single-dominant-pole model, SBOA418 figures 4-2 and 4-4.

Open-loop output impedance R_O (Ω)

Load capacitance C_L (nF)

Gain bandwidth (MHz)

Noise gain 1 + R_F/R_G (V/V)

R_ISO to evaluate (0 = optimum) (Ω)

Round up in

DC load current (mA)

Pole from C_L against R_O · loop bandwidth f_gbw / G: 159 kHz · 1.00 MHz
Without R_ISO: phase margin · overshoot: 22.5° · 53 % — unstable
Largest C_L this amplifier drives directly at 45°: 2.25 nF
R_ISO optimum (SBOA418 eq 2) · next E24 up: 48.6 Ω · 51.0 Ω
With 51.0 Ω: zero · pole · crossover: 312 kHz · 105 kHz · 411 kHz
With 51.0 Ω: phase margin · overshoot: 67.2° · 3 % — stable
Bandwidth at the load · DC drop at 1.00 mA: 312 kHz · 51.0 mV

10.0 nF against 100 Ω puts a pole at 159 kHz, below the 1.00 MHz loop bandwidth, and the loop reaches 0 dB at 40 dB/decade with 23° — SBOA626 calls under 35° unstable and 35–45° marginal. Direct drive is possible up to 2.25 nF; above that the resistor is the fix.

1.00 mA through 51.0 Ω drops 51.0 mV outside the loop. If the load needs DC accuracy, SBOA626's dual-feedback method (R_F from the load, C_F from the amplifier output) puts the resistor inside the loop at DC.

How this is calculated

Standard: TI SBOA418; TI SBOA626

$f_{p2} = \frac{1}{2\pi R_O C_{LOAD}}$: SBOA418 eq 3: the pole the load adds to the open-loop gain. Below f_gbw it makes the rate of closure 40 dB/decade.
$R_{ISO} = \frac{1 + \sqrt{1 + 8\pi R_O C_{LOAD} f_{gbw}}}{4\pi C_{LOAD} f_{gbw}}$: SBOA418 eq 2, SBOA626 eq 28: the zero placed at the closure frequency √(f_p2*·f_gbw). f_gbw is divided by the noise gain for a gain stage.
$f_{z1} = \frac{1}{2\pi R_{ISO} C_{LOAD}}, \qquad f_{p2}^{*} = \frac{1}{2\pi (R_O + R_{ISO}) C_{LOAD}}$: SBOA418 eq 4 and 5: the zero R_ISO adds and where it moves the pole.
$PM = 90^\circ - \arctan\frac{f_c}{f_{p2}^{*}} + \arctan\frac{f_c}{f_{z1}}$: Phase margin at the loop crossover f_c of a single-dominant-pole amplifier with the pole-zero network; f_c solved numerically.
$PO = e^{-\pi\zeta/\sqrt{1-\zeta^2}}, \qquad PM = \arctan\frac{2\zeta}{\sqrt{\sqrt{1+4\zeta^4} - 2\zeta^2}}$: Second-order overshoot from phase margin, the relation behind SBOA626 figure 2-16: 45° is 23 %, 30° is 41 %.
$C_{max} = \frac{\sqrt{2}}{2\pi R_O f_{gbw}}$: The load at which the bare margin is exactly 45°: the pole at f_gbw/√2.

Assumptions

R_O is flat and resistive across the amplifier's bandwidth, which SBOA418 states as the condition for the method; amplifiers with a complex Z_O need simulation.
The amplifier is a single dominant pole up to f_gbw. Secondary poles near f_gbw lower the real margin; the vendor's SPICE model is the check.
The feedback is taken from the amplifier's output pin, not the load side of R_ISO.
The load is a pure capacitance to ground; a resistive part in parallel damps the pole and makes the estimate conservative.
Overshoot assumes a second-order response, as SBOA626 §2.6 does for its conversion.

What sets whether an op amp survives a capacitive load

The ideal op amp has zero output impedance; the real one, SBOA418 says, has "a non-zero output impedance typically in the range of Ω to kΩ", and vendors plot it as R_O (or Z_O) against frequency. Put a capacitor on the output and "the load capacitance (C_LOAD) interacts with the output impedance of the amplifier (R_O), producing an additional pole in the amplifier's A_OL curve" at f_p2 = 1/(2π R_OC_LOAD). Below the gain bandwidth that pole makes the loop gain fall at 40 dB/decade where it crosses 1/β, "resulting in a total of 40 dB/decade rate of closure", and the phase margin collapses. The symptoms, from SBOA626's abstract: "overshoot and ringing in response to an input, load transients, and — in the worst cases — an oscillation that is continuous and independent of the input signal".

The fix the calculator sizes is the oldest one. A resistor R_ISO between the output and the capacitor, with the feedback still taken from the amplifier's output pin, "interacts with the load capacitance to produce a zero in the A_OL curve" at f_z1 = 1/(2π R_ISO C_LOAD), "canceling out the effect of f_p2, and restoring the rate of closure to 20 dB per decade". The pole moves slightly too, to 1/(2π (R_O + R_ISO) C_LOAD). SBOA418's contribution is where to put the zero: at the frequency where the loaded gain would cross 1/β, which sits at the geometric mean of the pole and the gain bandwidth. Solving that quadratic gives its equation 2, and "the optimal isolation resistance is the smallest series resistance that produces an acceptable transient response". SBOA626 calls the same equation its "design method for minimum R_ISO" and adds the rule for the parts bin: "when choosing a standard resistor value always round the resistance to a larger value".

The phase margins shown are from a single-dominant-pole model of the amplifier — an integrator crossing 0 dB at f_gbw/G followed by the pole and zero above — which is the model SBOA626 §4.1 uses and which reproduces its example (22.5°, 65°, 87°). The overshoot column converts each margin through the second-order relation SBOA626 §2.6 describes; it gives the pairs the paper quotes, "45° or less than 23 % overshoot", "30° or 41 % overshoot". The paper's thresholds are the verdicts: "TI recommends a phase margin ≥ 45° for stable circuits", 35–45° is "marginally stable", and "phase margin < 35° is unstable".

Isolation resistor chart

SBOA418's optimal R_ISO for a unity-gain buffer, computed by the calculator above, across the capacitive loads an op amp meets, from a cable's worth of picofarads to a reference's worth of microfarads. Two output resistances and two gain bandwidths bracket most general-purpose parts; the calculator takes the datasheet's exact figures.

C_L	R_O 100 Ω, GBW 1 MHz	R_O 100 Ω, GBW 10 MHz	R_O 50 Ω, GBW 1 MHz	R_O 50 Ω, GBW 10 MHz
100 pF	1.69 kΩ	229 Ω	1.64 kΩ	199 Ω
1 nF	229 Ω	48.6 Ω	199 Ω	37.3 Ω
10 nF	48.6 Ω	13.4 Ω	37.3 Ω	9.75 Ω
100 nF	13.4 Ω	4.07 Ω	9.75 Ω	2.90 Ω
1 µF	4.07 Ω	1.27 Ω	2.90 Ω	900 mΩ
10 µF	1.27 Ω	400 mΩ	900 mΩ	283 mΩ

The resistor falls as the load grows, which reads backwards until the mechanism is clear: a larger capacitor puts the load pole lower, and a smaller resistor is enough to place the cancelling zero below it. What grows instead is the DC drop across the resistor, which is why the microfarad rows belong to references with no load current.

Worked example: SBOA626's 100 Ω amplifier on 10 nF

The calculator's defaults are the white paper's §4.1 circuit: a buffer with R_O = 100 Ω, 1 MV/V of open-loop gain with a 1 Hz dominant pole — 1 MHz of gain bandwidth — driving 10 nF, and 1 mA of load current.

pole from the load     1 / (2π × 100 Ω × 10 nF)                  = 159 kHz   (SBOA626: "158kHz")
loop crosses 0 dB at   383 kHz, falling at 40 dB/decade
phase margin, bare     90° − atan(383 / 159)                     = 22.5°     (SBOA626: "PM = 22.5°")
largest direct load    √2 / (2π × 100 Ω × 1 MHz)                 = 2.25 nF for 45°
R_ISO optimum          (1 + √(1 + 8π × 100 × 10 nF × 1 MHz)) / (4π × 10 nF × 1 MHz)
                       = (1 + √26.1) / 0.1257                    = 48.6 Ω    (SBOA626: "48.6Ω")
zero  ·  pole          1/(2π × 48.6 × 10n) = 327 kHz  ·  1/(2π × 148.6 × 10n) = 107 kHz   (paper: 327 kHz, 107 kHz)
phase margin, 48.6 Ω   90° − atan(406/107) + atan(406/327)       = 65.9°     (paper's simulation: 65.1°)
next E24 up            51 Ω → 67°, 3 % overshoot, 51 mV drop at 1 mA
conservative, 181 Ω    zero 88 kHz, pole 57 kHz                  → 87°, no overshoot, 181 mV drop

The paper's transient plots say what the numbers mean: without the resistor "large overshoot and ringing"; with 48.6 Ω "a relatively small overshoot and good phase margin"; with 181 Ω "practically no overshoot and excellent phase margin". The price of the larger value is on the next page — R_ISO and C_L "form a low pass filter, so larger values of R_ISO reduces the bandwidth", "from 602 kHz for R_ISO = 0 Ω to 107 kHz for R_ISO = 181 Ω" — and in the DC drop, which sits outside the loop and is an error at the load.

The other case worth entering is SBOA418's: an OPA392 (R_O120 Ω, 13 MHz) as a reference buffer on 10 µF. The pole lands at 133 Hz, five decades below the bandwidth, and the margin is 0.2° — the note's simulation says "less than 1°". Equation 2 asks for 384 mΩ; "implementing a small 380 mΩ isolation resistor in the OPA392 buffer circuit improves the phase margin to 60°". The single-pole estimate says 52° for the same resistor, inside the "50°–60°" the note says the placement targets; the difference is the real amplifier's higher-order poles, which only its SPICE model knows. A 390 mΩ resistor, or a short trace, is the whole fix.

Where the isolation-resistor model stops being valid

R_O must be flat. SBOA418: "the analysis in this document applies to amplifiers that have a flat, resistive output impedance across the effective bandwidth". Many rail-to-rail and chopper amplifiers have a Z_O that rises or falls with frequency — SBOA626 spends its chapter 6 on the resonances a complex Z_O makes with the load — and for those the equation is a starting point for a simulation, not an answer.
The margin is an estimate. One dominant pole plus the RC network is the whole model. "Most op amps have additional poles and zeros near the unity gain bandwidth, so the phase margin is also impacted by the secondary poles" (SBOA626). Confirm with the vendor model, or with the paper's bench test: a 10 mV_pp square wave and the overshoot read against its figure.
The resistor is outside the loop. Any load current drops I_L × R_ISO that the amplifier does not correct. When that matters, SBOA626's dual-feedback method returns the DC feedback to the load side through R_F and keeps the high-frequency feedback at the output through C_F; SSZT999 compares its step response and noise with the plain resistor.
The tolerances are real. R_O varies with process and temperature, and "the minimum R_ISO also has less tolerance to process, temperature, and component variation". Where the bandwidth and the drop allow it, the conservative value — the zero a decade below the crossing — is the one that survives corners.
Capacitance on the inverting input is a different instability. It puts a zero in 1/β rather than a pole in A_OL, and the cure is a feedback capacitor, not R_ISO. SBOA626 chapter 5 covers it.

Common capacitive-load mistakes

Buffering a reference straight into its 10 µF. The pole is in the hundreds of hertz and no amplifier survives it unaided; the fix is well under an ohm.
Taking the feedback from the load side of R_ISO. That puts the resistor and the capacitor back inside the loop and the zero is gone; the feedback goes to the amplifier's output pin, or to the dual-feedback network.
Reading the datasheet's overshoot-vs-C_L plot for the wrong gain. The plots "specify the op amp configuration used to drive the capacitive load because the configuration affects the stability"; a G = +1 curve does not apply to a G = +10 stage, and the calculator's noise-gain field is that difference.
Choosing the resistor by feel. 1 kΩ "to be safe" on 10 nF corners at 16 kHz and drops a volt per milliamp; the equation says 49 Ω.
Measuring stability at the load. The overshoot that reports phase margin is at the amplifier's output pin; "to measure stability using AC gain peaking, the measurement must be made directly at the op amp output, not at the load".