Bootstrap capacitor calculator for high-side gate drivers

A high-side N-channel MOSFET needs a gate supply that rides on its source, and the bootstrap capacitor is that supply: charged from V_DD through a diode while the low side is on, floated up with the switch node while the high side is on. TI's SLUA887 sizes it two ways — ten times the gate's Q_g/(V_DD − V_F), or the full charge the gate and the driver take in the longest on-time divided by the headroom to the UVLO threshold — and sizes the bypass, the diode and the resistor around it. Enter the driver, the MOSFET and the switching conditions to get both minimums, the droop of the capacitor fitted, the start-up peak current, and whether the low-side window is long enough to recharge it.

Fig 1 — The bootstrap capacitor over two cycles at the maximum duty cycle. While the low side is on it charges to V_DD − V_F, 11.3 V; while the high side is on it supplies the gate charge and the driver's leakage and quiescent current, and droops 511 mV. The droop has to stop above the driver's UVLO falling threshold, 8.00 V, or the high-side switch is turned off mid-pulse.

Driver supply V_DD (V)

Bootstrap diode V_F (V)

HB UVLO falling threshold (V)

High-side gate charge Q_g (nC)

HB leakage I_HBS (µA)

HB quiescent I_HB (µA)

Switching frequency (kHz)

Maximum duty cycle

Bootstrap resistor (Ω)

Bootstrap capacitor (0 = minimum) (nF)

Gate capacitance Q_g / (V_DD − V_F) · 10× rule (SLUA887 eq 2): 4.42 nF · 44.2 nF
Charge per on-time: gate + leakage + quiescent · headroom to UVLO: 51.1 nC · 3.30 V
C_boot minimum: detailed (eq 3) · the larger of the two: 15.5 nF · 44.2 nF
With 100 nF: droop per on-time · V_DD bypass ≥ 10×: 511 mV (4.5 %) · 1.00 µF
R_boot 2.20 Ω: start-up peak · τ at D · charged in 3τ · low-side window: 5.14 A · 244 ns · 733 ns · 1.00 µs
Energy in the first charge, dissipated in R_boot: 6.38 µJ

SLUA887 on the diode: fast recovery or Schottky, "with low forward voltage drop and low junction capacitance", rated above the bus; reverse recovery on the switch-node edge "can trigger the driver's UVLO". On the resistor: 5.14 A is the start-up peak into the diode, and the note's scope shots show 0 Ω ramping HB-HS fast enough to disturb both outputs where 2.2 Ω did not.

How this is calculated

Standard: TI SLUA887A; Nexperia AN90059

$C_g = \frac{Q_g}{V_{DD} - V_F}, \qquad C_{boot} \geq 10\,C_g$: SLUA887 eq 1 and 2: the rule of thumb, "without being depleted by more than 10 %".
$C_{boot} \geq \frac{Q_G + I_{HBS}\,D_{max}/f_{sw} + I_{HB}/f_{sw}}{V_{DD} - V_{DH} - V_{HBL}}$: SLUA887 eq 3: gate charge plus the driver's leakage and quiescent charge over the longest on-time, against the headroom to the UVLO falling threshold.
$C_{VDD} \geq 10\,C_{boot}$: Eq 5: the bypass the recharge comes from, for 10 % ripple on it.
$I_{pk} = \frac{V_{DD} - V_F}{R_{boot}}, \qquad \tau = \frac{R_{boot} C_{boot}}{D}, \qquad t_{charge} \approx 3\tau, \qquad E = \tfrac{1}{2} C_{boot} V^2$: Eq 9, 6, 8 and 7: the start-up peak the resistor limits, the charging time constant during the off-time, and the first charge's energy the resistor absorbs.

Assumptions

The capacitor recharges fully each cycle when the low-side window exceeds three time constants; the recharge path is treated as R_boot alone.
C_boot is the capacitance at the working voltage; ceramic DC-bias loss is not applied.
The gate charge is the datasheet Q_g at the drive voltage; the driver's own output-stage losses are not added.
The detailed equation uses the maximum duty cycle as the longest on-time; skipped cycles are covered only by the 10× margin.
Diode reverse recovery and negative switch-node transients are not modelled.

What sets the bootstrap capacitor

An N-channel MOSFET on the high side of a bridge has its source on the switch node, so "to keep the MOSFET on, V_drive needs to be larger than V_dd" (Nexperia AN90059). The bootstrap circuit makes that supply from two parts. SLUA887: "when the low-side FET is on (high-side FET is off), the HS pin and the switch node are pulled to ground; the V_DD bias supply, through the bypass capacitor, charges the bootstrap capacitor through the bootstrap diode and resistor." When the high side turns on and the switch node rises, the diode blocks and the capacitor rides up with it as "a floating voltage supply for the high side driver circuit for the duration that the MOSFET is on" (AN90059).

The capacitor is the design decision. "From a design perspective, this is the most important component because it provides a low impedance path to source the high peak currents to charge the high-side switch." SLUA887 gives two sizes. The rule of thumb: the gate looks like a capacitance Q_g / (V_DD − V_F), and "this bootstrap cap should be at least 10 times greater than the gate capacitance of the high-side FET", so that it is not "depleted by more than 10 %" — the factor covers "capacitance shift from DC bias and temperature, and also skipped cycles that occur during load transients". The detailed version adds what the driver itself takes during the on-time — the HB leakage over the maximum duty cycle and the HB quiescent current over a period — and divides the total charge by the headroom between the charged capacitor and the driver's UVLO falling threshold. The calculator computes both and takes the larger; at low switching frequency or high duty cycle the driver's own current wins, which is the case AN90059 sends to a charge pump.

Around it: the V_DD bypass "should be sized to be at least 10 times larger than the bootstrap capacitor so that it is not completely drained during the charging time"; the diode "a fast recovery diode or Schottky diode with low forward voltage drop and low junction capacitance", rated above the bus, because its reverse recovery on the switch-node edge "can trigger the driver's UVLO and shutdown the gate driver"; and the resistor, which limits the start-up peak (V_DD − V_F)/R_boot at the cost of a time constant R_bootC_boot/D and takes the first charge's ½CV² as heat.

Worked example: 50 nC at 100 kHz from a 12 V driver

The defaults: a 12 V driver with a 0.7 V diode and an 8 V UVLO falling threshold, a high-side MOSFET of 50 nC, 10 µA of HB leakage and 100 µA of HB quiescent current, 100 kHz at up to 90 % duty, 2.2 Ω in series, and 100 nF fitted.

gate capacitance   50 nC / (12 − 0.7) V                    = 4.42 nF
10× rule           10 × 4.42 nF                             = 44.2 nF
charge per on-time 50 nC + 10 µA × 0.9 / 100 kHz + 100 µA / 100 kHz = 50 + 0.09 + 1.0 = 51.1 nC
headroom           12 − 0.7 − 8                             = 3.3 V
detailed minimum   51.1 nC / 3.3 V                          = 15.5 nF     (the 10× rule is larger: 44.2 nF)
fitted 100 nF      droop 51.1 nC / 100 nF                   = 511 mV, 4.5 % — above UVLO
V_DD bypass        10 × 100 nF                              = 1 µF
R_boot 2.2 Ω       peak 11.3 V / 2.2 Ω = 5.1 A;  τ = 2.2 × 100 nF / 0.9 = 244 ns;  3τ = 733 ns
low-side window    (1 − 0.9) / 100 kHz                      = 1.0 µs  — enough to recharge
first charge       ½ × 100 nF × 11.3²                       = 6.4 µJ in the resistor

At 100 kHz the gate charge dominates and the 10× rule sets the part; change the frequency to 1 kHz and the duty to 0.98 and the quiescent current's 100 µA takes a microcoulomb per cycle, the detailed equation asks for over 300 nF, and the capacitor's job has changed from driving the gate to holding the driver alive. AN90059 draws that line: "there is a minimum allowed switching frequency and a maximum allowed duty cycle. A larger value capacitor is required when operating at lower switching frequencies or higher duty cycles or both."

Where the bootstrap model stops being valid

DC is impossible. A bootstrap supply must be recharged, so the high side cannot stay on. SLUA887's drivers "cannot operate at very high duty cycles because a minimum pulse width at LO is necessary to allow replenishment" (Infineon says the same); for 100 % duty AN90059's charge pump "has no minimum frequency or maximum duty cycle limitations".
The capacitance is the capacitance at voltage. A class 2 ceramic at 12 V can be half its label; the 10× margin is partly for that. Use the derated value, or a C0G.
The recharge is not a clean RC. Charging through the diode and the low-side switch's R_DS(on) from a bypass that is itself drooping; the 3τ figure is SLUA887's estimate, not a waveform.
Negative switch-node transients. Infineon: the VS pin "swings below the level of the negative DC bus due to the parasitic inductances", and drivers carry a negative-VS rating the layout has to respect. None of that is in the sums.
Layout is the other half. SLUA887's high-current loop is "the bootstrap capacitor, the bootstrap diode, the ground-referenced VDD bypass capacitor of the driver, and the low-side power switch"; the capacitors "should be placed as closed as possible to the gate driver supply pins".

Common bootstrap mistakes

Sizing for the gate charge alone. At low frequency or high duty the driver's quiescent current is the load; the detailed equation, not the 10× rule, is the one to check.
A slow diode. Reverse recovery on the switch-node edge dumps charge back into V_DD and rings HB-HS; SLUA887's scope shots are of exactly that.
No bootstrap resistor at all. 0 Ω gave SLUA887's driver a start-up ramp fast enough to disturb both outputs; 2.2 Ω did not.
A V_DD bypass the same size as C_boot. The recharge comes from it; at 1:1 it halves.
Ignoring the UVLO threshold. The headroom is V_DD − V_F − V_HBL, and on a 10 V driver with an 8 V UVLO it is 1.3 V, not 10.