Coplanar waveguide impedance calculator: CPW and grounded coplanar (GCPW)

Silicon Labs' 50 Ω grounded coplanar line is a 0.45 mm trace with 0.25 mm gaps. It sits on 0.3 mm of ε_r 4.6 FR-4 above a ground plane. Height to the plane sets the width: on a 1.6 mm board, the same gaps need 1.25 mm. The model assumes bare copper, so solder mask over the line lowers Z₀.

Characteristic impedance and effective permittivity of a coplanar waveguide, a signal trace between two ground pours on the same layer, with a ground plane below it (grounded coplanar, GCPW or CPWG) or without one; the signal width or the gap that lands on a target impedance; and the delay, the wavelength and the layout rules that come with the line. The defaults are the 50 Ω line Silicon Labs publishes for its 2.4 GHz radio boards.

Fig 1 — Grounded coplanar waveguide: Z₀ 51.9 Ω, ε_eff 2.96, for W 0.45 mm, G 0.25 mm, H 0.3 mm, T 0.035 mm, εr 4.6. H and T are not drawn to scale.

Solve for

Line type

Length unit

Signal trace width W (mm)

Gap to the coplanar ground G (mm)

Dielectric height to the plane below H (mm)

Copper thickness T (mm)

Relative permittivity (εr)

Frequency f (GHz)

Characteristic impedance Z₀: 51.9 Ω
Z₀ at zero thickness · Δ (Qucs 12.16): 53.3 Ω · 0.0847 mm
Effective permittivity: 2.963 · 3.216 at T = 0
Velocity · delay: 0.581 c · 5.74 ps/mm · 146 ps/in
Wavelength λ at 2.4 GHz · λ/16 (AN928): 72.6 mm · 4.54 mm
Via pitch, λ/10 at 24 GHz (AN928): 0.726 mm in ε_eff · 1.25 mm in air
No plane below · infinitely thick: 71.0 Ω · 65.3 Ω
Filling factor q · moduli: 0.616 · k₁ 0.474 · k₃ 0.838
Coplanar ground width (Sandia Eq 34): > 0.475 mm each side
Line-to-line ground (Sandia Eq 35): > 1.90 mm for 30 dB
H / 2(W + 2G) (Sandia Eq 36): 0.16
TE₀ cut-off (Qucs 12.24): 131.7 GHz · f/f_TE 0.018

A quasi-static conformal-mapping result for bare copper. Solder mask over the line adds capacitance and lowers Z₀; for a production board, take the fabricator's field-solver figure for its own stackup and mask, and adjust W or G to it.

How this is calculated

Standard: Qucs technical documentation, Coplanar waveguides (after Gupta et al.); Sandia SAND2017-12410J

$k_1 = \frac{W}{W + 2G}, \qquad \varepsilon_{re} = \frac{\varepsilon_r + 1}{2}, \qquad Z = \frac{30\pi}{\sqrt{\varepsilon_{re}}}\cdot\frac{K'(k_1)}{K(k_1)}$: Qucs 12.6–12.7, Sandia Eq 3, 7 and 10: the coplanar waveguide on an infinitely thick substrate, with half the field in air and half in the dielectric. K is the complete elliptic integral of the first kind and K′(k) = K(√(1 − k²)). Only the ratio W/(W + 2G) appears. In air with k₁ = 1/√2, K′ = K and Z = 30π = 94.25 Ω exactly.
$\varepsilon_{re} = 1 + \frac{\varepsilon_r - 1}{2}\cdot\frac{K(k_2)}{K'(k_2)}\cdot\frac{K'(k_1)}{K(k_1)}, \qquad k_2 = \frac{\sinh\left(\pi W / 4H\right)}{\sinh\left(\pi (W + 2G) / 4H\right)}$: Qucs 12.8–12.9: a substrate H thick with nothing below it. Only the effective permittivity changes, and the impedance is 12.7 with this ε_re. As H grows, k₂ tends to k₁ and ε_re to (ε_r + 1)/2.
$\begin{aligned} k_3 &= \frac{\tanh\left(\pi W / 4H\right)}{\tanh\left(\pi (W + 2G) / 4H\right)}, \qquad q = \frac{K(k_3)/K'(k_3)}{K(k_1)/K'(k_1) + K(k_3)/K'(k_3)} \\ \varepsilon_{re} &= 1 + q\,(\varepsilon_r - 1), \qquad Z = \frac{60\pi}{\sqrt{\varepsilon_{re}}}\cdot\frac{1}{K(k_1)/K'(k_1) + K(k_3)/K'(k_3)} \end{aligned}$: Qucs 12.10–12.13: the conductor-backed line, "an hybrid between microstrip and true CPW mode". Sandia Eq 17 gives the same ε_eff in another arrangement. Sandia Eq 18, the impedance, is printed with a denominator of K′(k)/K(k) · K(k_G)/K′(k_G) alone; with the "1 +" of its own Eq 17 restored, and the factor K′(k)/K(k) in front, it is this equation, and as printed it would tend to 60π/√ε_eff for every geometry as H grows. The unit tests check both. q is 0.616 for the Silicon Labs line.
$\begin{aligned} \Delta &= \frac{1.25\,T}{\pi}\left(1 + \ln\frac{4\pi W}{T}\right), \qquad k_e = \frac{W + \Delta}{(W + \Delta) + 2(G - \Delta)} \\ \varepsilon_{re}^{t} &= \varepsilon_{re} - \frac{0.7\,(\varepsilon_{re} - 1)\,T/G}{K(k_1)/K'(k_1) + 0.7\,T/G} \end{aligned}$: Qucs 12.14–12.18, a first-order correction for copper thickness from Gupta et al.: the edges move by Δ, k_e replaces k₁ in the impedance, and the extra air between the thick edges lowers ε_re. Qucs writes the gap as s. For the Silicon Labs line Δ = 0.0847 mm. Applied here to the grounded line as well, with k₃ unchanged.
$v = \frac{c}{\sqrt{\varepsilon_{re}}}, \qquad t_{pd} = \frac{\sqrt{\varepsilon_{re}}}{c}, \qquad \lambda = \frac{c}{f\sqrt{\varepsilon_{re}}}, \qquad c = 299\,792\,458\ \mathrm{m/s}$: Sandia Eq 1 in its terms, with c exact by the SI definition of the metre (Sandia rounds it to 3 × 10⁸ m/s). 5.74 ps/mm on the Silicon Labs line.
$W_G > \frac{W + 2G}{2}, \qquad d > (W_1 + 2G_1) + (W_2 + 2G_2), \qquad H \gg 2\,(W + 2G)$: Sandia Eq 34, 35 and 36, as rules of thumb: the width of each coplanar ground (Eq 34 is written (W + 2G + 2W_G)/(W + 2G) > 2), the ground between two lines for more than 30 dB isolation, and the distance a plane below must keep for the line to stay a pure coplanar waveguide.
$f_{TE} = \frac{c}{4H\sqrt{\varepsilon_r - 1}}$: Qucs 12.24: the cut-off of the TE₀ surface mode of the substrate, the frequency scale of the dispersion the quasi-static model leaves out.

Assumptions

Quasi-static: the impedance and ε_eff do not change with frequency. Dispersion is small well below f_TE and grows toward it.
Bare copper in air. Solder mask or any coating over the line adds capacitance and lowers Z₀; the model does not include it.
The coplanar grounds are infinitely wide (Sandia: "the effect of the finite ground plane and the metal thickness has not been considered"). Keep each wider than Sandia Eq 34 asks.
The thickness correction is first order. It is applied to the grounded line by the same substitution Qucs gives for the CPW, which is this page's reading rather than a statement in the sources; the result is flagged when T is more than 0.2 of G or of W, a threshold of this page.
The grounded line assumes an unbroken plane at H, tied to the side grounds by vias close enough that the grounds stay at one potential. The no-plane line assumes nothing conductive within 5 × 2(W + 2G) below, this page's reading of the "≫" in Sandia Eq 36.
Symmetric gaps, one homogeneous dielectric, lossless conductors. The width for a target is found by bisection: Z₀ falls monotonically as W grows.

What sets a coplanar waveguide's impedance

A coplanar waveguide is a signal trace with a ground pour on each side of it on the same layer, separated from them by two equal gaps. The field runs from the edges of the signal across the gaps to the grounds, partly through the air above the board and partly through the dielectric below. Sandia's report describes it as "a main center conductor and two ground conductors situated on either side of the center conductor separated by gaps", first proposed by C. P. Wen. Here W is the signal width, G each gap and H the dielectric height below the line, the letters Sandia uses, and T the copper thickness.

On a substrate so thick that nothing below matters, the line reduces to one number: the modulus k₁ = W/(W + 2G). Conformal mapping folds the gaps into a parallel-plate capacitor whose capacitance is a ratio of complete elliptic integrals, K′(k₁)/K(k₁), and the impedance is 30π/√ε_eff times that ratio, with ε_eff = (ε_r + 1)/2 because half the field is in air and half in the dielectric. Nothing else appears. Sandia puts it plainly: "the characteristic impedance of the CPW is not a function of the transmission dimensions, instead a function of the ratio of the dimensions." A 0.1 mm trace with 0.05 mm gaps on ε_r 4.6 is 72.1 Ω, and so is a 1 mm trace with 0.5 mm gaps (72.1 Ω). In air, a line with k₁ = 1/√2 has K′ = K and an impedance of exactly 30π = 94.25 Ω, which is one of the unit tests behind this page.

That freedom is what makes coplanar lines attractive on chips: the report notes that the size "can be chosen based on the power handing needs and acceptable attenuation level, independent of the line impedance." A printed circuit board takes some of it away, because a board almost always has copper underneath. When there is a plane at a height H, part of the field goes down to it instead of to the side grounds, which adds capacitance and lowers the impedance. The Qucs documentation handles that case with a second modulus, k₃, built from tanh(πW/4H) and tanh(π(W + 2G)/4H), and a filling factor q that says how the capacitance divides between the two regions; the wave, in its words, "is an hybrid between microstrip and true CPW mode." This is the grounded coplanar waveguide, GCPW or CPWG, and it is the line almost every RF board actually has. The calculator's default is one: q = 0.62 for the Silicon Labs line, against 0.5 for the ideal line with no plane.

The two effects pull in opposite directions as H changes. A thick dielectric with nothing below it is the ideal line. Remove copper from under a thin board and the dielectric thins out: less of the field is in the laminate, ε_eff falls toward 1 and the impedance rises; the Silicon Labs geometry with no plane below reads 71.0 Ω against 65.3 Ω for the ideal line. Put a plane at the same H and it reads 51.9 Ω. So a coplanar line on a PCB is designed for the plane it will actually have, and the line-type select above is the first input to get right.

Grounded coplanar waveguide width chart for 50 Ω

The signal width for 50 Ω, grounded, at five gaps and the dielectric heights common stackups put under the top layer, from the calculator's bisection at ε_r = 4.6 (Silicon Labs' figure for its FR-4) with 35 µm copper. The last column is the width a plain microstrip needs on the same height, from the IPC-2141 closed form themicrostrip impedance calculatoruses. On a multilayer board H is the dielectric between the top layer and the first inner plane; on a 2-layer board it is the whole board.

H	G = 0.15 mm	G = 0.2 mm	G = 0.25 mm	G = 0.3 mm	G = 0.5 mm	Microstrip
0.1 mm thin prepreg, 4+ layers	0.17	0.19	0.19	0.20	0.20	0.14
0.2 mm prepreg, 4 layers	0.30	0.33	0.35	0.36	0.38	0.32
0.3 mm AN928.2 board	0.39	0.45	0.48	0.51	0.55	0.50
0.36 mm prepreg, 4 layers	0.44	0.51	0.55	0.58	0.65	0.61
0.8 mm 0.8 mm 2-layer	0.63	0.80	0.92	1.02	1.23	1.42
1 mm 1.0 mm 2-layer	0.67	0.88	1.03	1.15	1.44	1.78
1.6 mm 1.6 mm 2-layer	0.73	1.02	1.25	1.43	1.93	2.88

Read it by rows and the plane dominates on thin dielectrics: at H = 0.1 mm the width only moves from 0.175 mm to 0.205 mm across the whole range of gaps, because the field goes down to the plane and the side grounds hardly see it. Read it at the bottom and the side grounds are doing the work: on a 1.6 mm two-layer board, 0.25 mm gaps bring the 50 Ω width to 1.25 mm, where a microstrip on the same board needs 2.88 mm. That is the reason coplanar lines are common on two-layer RF boards: without the side grounds, a 50 Ω line on a thick board is several times wider than the pads of the small parts it connects.

The top rows need a caution. At H = 0.1 and 0.2 mm the microstrip column is narrower than the coplanar ones, which cannot be physics: side grounds only add capacitance, so a coplanar line always needs a narrower trace than a microstrip on the same stackup, as it does from 0.3 mm down the table. It is the two models disagreeing where the copper is thick beside the dielectric. 35 µm is 35 % of a 0.1 mm prepreg; the IPC-2141 fit takes the copper into its (0.8W + T) term at full weight, while the coplanar thickness correction acts only on the edges facing the gaps and leaves the field to the plane as if the copper were flat. On dielectrics that thin, neither closed form is a substitute for the fabricator's field solver.

Coplanar waveguide impedance against the gap

Silicon Labs' layout notes say of their line that the "Characteristic impedance is not “super sensitive” to the gap value. It should be between 0.25 and 0.4 mm to have 47 through 53 Ω impedance." The table runs their W = 0.45 mm and H = 0.3 mm through the calculator, grounded, with 35 µm copper, over a wider range of gaps.

G (mm)	Z₀ (Ω)	ε_eff	q
0.15	46.8	2.79	0.59
0.20	49.9	2.89	0.60
0.25	51.9	2.96	0.62
0.30	53.2	3.02	0.63
0.35	54.2	3.08	0.64
0.40	55.0	3.12	0.64
0.50	56.1	3.19	0.66
0.75	57.7	3.32	0.68
1.00	58.7	3.40	0.70
2.00	60.7	3.58	0.74

Between 0.25 and 0.4 mm the model moves by 3.1 Ω, from 51.9 to 55.0 Ω, so it agrees that the gap is a weak lever there, and it moves less than the 6 Ω span the notes give. The plane is the reason: with it only 0.3 mm down, field that stops crossing a wider gap goes down to the plane instead, so the capacitance falls slowly. The q column shows the same thing from the other side: the wider the gap, the larger the share of the field that sits in the dielectric on its way to the plane. Below about 0.2 mm the side grounds start to matter and the impedance falls faster; beyond 1 mm they hardly matter at all, and the line is approaching a microstrip. That asymmetry is useful: a gap chosen a little wider than the minimum costs very little impedance, and a narrow gap is the feature a fab's etching varies most in proportion.

Worked example: Silicon Labs' 50 Ω grounded coplanar line

Silicon Labs publishes one line for its EFR32 radio boards, in AN928.2 Table 3.1 (and in AN928.1 Table 2.1 with a slightly thicker dielectric): ε_r 4.6, H 0.3 mm, G 0.25 mm, W 0.45 mm, copper 0.018 to 0.035 mm, for 2.4 GHz. Its notes define H: "For PCBs with more than 2 layers, 'H' is the distance between the top and the first inner layer. For 2-layer PCBs, 'H' is the distance between the top and the bottom layer." Through Qucs 12.10–12.13 and the thickness correction, step by step:

k1        W/(W + 2G) = 0.45/0.95                     = 0.4737
k3        tanh(π·0.45/1.2) / tanh(π·0.95/1.2)        = 0.8384
q         filling factor, 12.11                       = 0.6156
ε_re      1 + q(4.6 − 1), 12.10                       = 3.216
Z, T = 0  12.13                                       = 53.3 Ω
Δ         (1.25·0.035/π)(1 + ln(4π·0.45/0.035))       = 0.0847 mm
k_e       (W + Δ)/((W + Δ) + 2(G − Δ))                = 0.6180
ε_re^t    12.18                                       = 2.963
Z, 35 µm  12.13 with k_e                              = 51.9 Ω
Z, 18 µm  the same at T = 0.018 mm                    = 52.5 Ω

So the model reads the published 50 Ω line as 51.9 Ω with 35 µm copper, 52.5 Ω with 18 µm and 53.3 Ω with none. The Series 1 board's 0.325 mm dielectric reads 53.5, 54.2 and 55.1 Ω. The thickness correction is worth 2.6 % here: the copper's side walls face each other across the gap, adding capacitance, and the air between them lowers ε_eff from 3.216 to 2.963.

The remaining difference from 50 Ω is stated here rather than tuned away. The model is a quasi-static result for bare copper; the radio boards have solder mask over the line, which fills part of the gap and the space above it with a dielectric and lowers the impedance, in the direction of the difference. He and Tang's IPC paper puts a number on it only for surface microstrip: some fabricators "first calculate the impedance of surface microstrip line and multiply this value by an empirical coefficient such as 0.94 or 0.96 to get the impedance of coated microstrip line". The paper's own test lines are conductor-backed coplanar waveguides, but it measures their loss, not their impedance, so no source here gives the coplanar factor. As an illustration only, the same two factors applied to the 51.9 Ω here would give 48.8 to 49.8 Ω, which brackets 50 Ω; this page does not claim that the mask accounts for the whole difference. The notes themselves say "Different impedance calculators may yield slightly different results." To land the model exactly on 50 Ω at this height and copper, the gap would have to close to 0.201 mm, or the signal widen to 0.483 mm; for the 0.325 mm board the gap for 50 Ω is 0.177 mm. For a production board the right number is the fabricator's field-solver result for its own stackup and mask, and the width or gap adjusted to it.

The same line gives the rest of the layout. At 2.4 GHz the wavelength on it is 72.6 mm, so λ/16 is 4.54 mm. That is the length Silicon Labs uses as the dividing line: "A general rule is to use 50 Ω transmission lines where the length of the RF trace is longer than λ/16 at the fundamental frequency." The delay is 5.74 ps per millimetre. By Sandia's Eq 34 each coplanar ground should be wider than (W + 2G)/2 = 0.475 mm, and by Eq 35 two such lines sharing a ground need more than 1.90 mm of it between their gaps for 30 dB of isolation. And by Eq 36, H = 0.3 mm is far from ≫ 2(W + 2G) = 1.90 mm: this is unambiguously a grounded line, which is how Silicon Labs designs it.

Coplanar waveguide vs microstrip

On the Silicon Labs stackup, the same 0.45 mm trace without the side grounds is a microstrip, and the IPC-2141 closed form gives it 53.7 Ω, against 51.9 Ω as a grounded coplanar line with 0.25 mm gaps. The microstrip width for 50 Ω on that height is 0.504 mm; the coplanar width is 0.483 mm. On a thin dielectric the two lines are close, because the plane below carries most of the field either way. The two figures come from different models, a curve fit for the microstrip and conformal mapping for the coplanar line, so a difference of an ohm or two between them is model, not physics.

The differences that matter are elsewhere. A coplanar line brings its return path up to the surface beside the signal, so shunt parts, ESD diodes and connector grounds land on the same layer a few tenths of a millimetre away. Its field is contained between the grounds, which Silicon Labs names as the reason to use it: grounded coplanar lines reduce "sensitivity to PCB thickness variations" and "radiation and coupling effects". And on a thick board it is the only way to a manageable 50 Ω width, as the chart shows: 1.25 mm with 0.25 mm gaps on 1.6 mm FR-4, against 2.88 mm for the microstrip. The price is the via fence and the discipline of keeping the gaps clear.

Where the quasi-static model stops being valid

Frequency. Sandia notes that because the phase velocity differs in the air and in the substrate, "the CPW cannot support a pure Transverse Electro-Magnetic (TEM) propagation mode", and the formulas here are quasi-TEM: ε_eff and Z₀ do not depend on frequency. Qucs gives the frequency scale on which that breaks down, the TE₀ cut-off of the substrate, f_TE = c/(4H√(ε_r − 1)). For H = 0.3 mm of ε_r 4.6 it is 132 GHz, so 2.4 GHz is at 0.018 of it; Qucs's dispersion expression (12.19), presented for the CPW and used here only as an indication for the grounded line, raises ε_eff by 0.03 % at 2.4 GHz. On a 1.6 mm board f_TEfalls to 24.7 GHz, and the same expression puts the 50 Ω line there (1.25 mm wide, 0.25 mm gaps) 0.8 % higher in ε_eff at 6 GHz than the quasi-static figure, and the difference grows quickly with frequency. Qucs claims better than 5 % for its dispersion expression within 0.1 ≤ W/H ≤ 5, 0.1 ≤ W/G ≤ 5, 1.5 ≤ ε_r ≤ 50 and f/f_TE ≤ 10.

Metal thickness. The conformal mapping assumes copper of zero thickness, and Sandia leaves thickness out entirely. Qucs adds it as a first-order correction, with the remark that "In most practical cases, the strips are very thin, yet their thickness cannot be entirely neglected." Sandia explains when it stops being small: "At small feature size, the metal thickness is larger fraction of the line dimensions, so its effect may not be ignored in the characteristic impedance calculation." On a PCB the gap is the smallest feature, and 35 µm of copper beside a 0.1 mm gap is a third of it. Neither source gives a limit for the correction; this page flags the result when T exceeds 0.2 of G or of W, and refuses it when the correction's Δ is as wide as the gap.

Very wide gaps. As G grows the side grounds stop mattering and the line becomes a microstrip, but the conformal model does not become a good microstrip model on the way. On the Silicon Labs stackup it gives 60.7 Ω at G = 2 mm, where the IPC-2141 fit gives 53.7 Ω for the same trace with no side grounds at all. Once the gap is several times H, the side grounds are decoration, and the microstrip calculatoris the right tool.

Finite coplanar grounds. The formulas assume the side grounds extend to infinity. Sandia: "the effect of the finite ground plane and the metal thickness has not been considered in the analyses presented," and for a real layout, "It is necessary to provide enough conductor to maintaining the current profile of the CPW, and to allow the electric field lines to terminate." Its rule of thumb, Eq 34, is a ground on each side wider than (W + 2G)/2. A ground sliver between the line and a neighbouring pour, narrower than that, is not the ground the model assumes.

Other modes, and the vias. A coplanar line has three conductors, and more when there is a plane below. Sandia: "CPW is a multi-conductor transmission line. It can support a mode between any combination of these conductors. Hence CPW is prone to excitation of non-CPW modes. For example, slot line modes can be supported by the two top ground conductors and/or, the center conductor and one of the ground conductors." The cure on a chip is to tie the two grounds together: "A CPW can be thought of two coupled slot lines in parallel, and it is necessary to keep currents in these two slots balanced," and "This ground connection needs to be repeated at least at every quarter wavelength of the highest operating frequency." On a board the vias from each side ground to the plane below do that job, since they tie both grounds to the same plane. Silicon Labs asks for "many vias near the coplanar lines in order to minimize radiation" without giving a pitch for them; the pitch it does give is for stitching vias along ground-pour edges: "The maximum distance between the vias should be less than lambda/10 of the 10th harmonic (the typical distance between vias on reference radio boards is 40–50 mil)." For a 2.4 GHz radio that is λ/10 at 24 GHz: 0.73 mm in this line's ε_eff, 1.25 mm (49 mil) in free space. The note does not say which it means; the reference boards' 40–50 mil matches the free-space figure, and the dielectric figure is the stricter of the two.

Solder mask and the laminate. Everything here is bare copper on a homogeneous dielectric with one value of ε_r. Solder mask over the line, glass weave, resin-rich regions near the surface and the fall of ε_r with frequency all shift the result by amounts that depend on the fabricator's materials. That is why the worked example above lands a few percent from the published 50 Ω, and why the number that goes on the fab drawing should be the fab's.

Common coplanar waveguide mistakes

Using the board thickness as H on a multilayer board. The plane that matters is the first one below the top layer, and on a four-layer board it is a few tenths of a millimetre down, not 1.6 mm. Silicon Labs' definition of H is quoted in the worked example.
Copying a reference design's W and G onto a different stackup. The notes warn: "A 2-layer PCB requires different parameters for a 50 Ω transmission line than shown in this table due to the different value of "H"." On a 1.6 mm two-layer board the 0.45 mm / 0.25 mm line reads 69.5 Ω; 50 Ω there needs a 1.25 mm signal.
Calculating a line with a plane below as plain coplanar. On the Silicon Labs stackup the no-plane formula gives 71.0 Ω for a line that is 51.9 Ω. Sandia's Eq 36 is the test: only when H ≫ 2(W + 2G) can the plane be ignored.
Leaving the side grounds unstitched, or stitching them sparsely. The grounds then float relative to each other and to the plane, the slot-line modes Sandia describes can be excited, and the edges radiate.
Narrow ground slivers. A coplanar ground narrower than (W + 2G)/2, 0.475 mm for the Silicon Labs line, is not the ground the formulas assume, and a thin sliver with a via at each end is an antenna of its own.
Running two lines side by side on one shared ground strip. Sandia's Eq 35 asks for more than (W₁ + 2G₁) + (W₂ + 2G₂) of ground between them for 30 dB of isolation, 1.90 mm for two Silicon Labs lines.
Chasing the gap to fix an impedance on a thin dielectric. As the gap table shows, on H = 0.3 mm the gap from 0.25 to 0.4 mm moves the line by only 3.1 Ω; the width and the dielectric height are the stronger levers.
Treating the calculator's figure as the fab's. The notes say it directly: "Different impedance calculators may yield slightly different results." Order controlled impedance and let the fab set the final width.