I2C pull-up resistor calculator

An I²C pull-up has a floor and a ceiling. Too small and the driver cannot sink enough current to pull the line down to a valid low. Too large and the line cannot rise fast enough through the bus capacitance for the mode you picked. Pick something in the window; the geometric middle is a fine default.

Fig 1 — Pull-up window 967 Ω to 3.5 kΩ.

Bus mode

Supply voltage (V)

Bus capacitance

Total bus capacitance (pF)

Chosen pull-up (Ω)

Driver V_OL (V)

Minimum (V_OL at rated sink): 967 Ω
Maximum (rise time): 3.54 kΩ
Suggested E24 value: 1.80 kΩ · 153 ns rise
Rise time with 2.20 kΩ: 186 ns
Low-level current per line: 1.32 mA
Pull-up power, both lines low: 8.70 mW
Time constant R·C_b: 220 ns

How this is calculated

Standard: NXP UM10204 Rev 7 Section 7.1, Table 10; TI SLVA689

$R_{p(min)} = \frac{V_{DD} - V_{OL}}{I_{OL}}$: The sink current is 3 mA in Standard and Fast mode, 20 mA in Fast-mode Plus, and V_OL is 0.4 V.
$R_{p(max)} = \frac{t_r}{0.8473 \cdot C_b}$: Maximum rise time is 1000 ns in Standard mode, 300 ns in Fast mode and 120 ns in Fast-mode Plus.
$0.8473 = \ln\!\left(\frac{0.7}{0.3}\right)$: The 30 % to 70 % portion of an RC rise, in time constants.
$t_r = 0.8473 \cdot R_p \cdot C_b$: Rise time of a pull-up you have already picked.
$I_{low} = \frac{V_{DD} - V_{OL}}{R_p}, \quad P = V_{DD} \cdot I_{low}$: Current and power while one line is held low. SDA and SCL each have a pull-up, so a bus pays this twice.
$C_b = N_{devices} \cdot C_{pin} + L_{trace} \cdot C_{\text{per length}} + C_{other}$

Assumptions

Bus capacitance is the total: every pin, pad and trace on SDA (or SCL). Budget 5-10 pF per device plus about 1 pF per cm of trace if you have not measured it.
V_OL of 0.4 V is the specification value for buses above 2 V; at or below 2 V the specification says 0.2·V_DD instead — 0.36 V on a 1.8 V bus — so enter that. A driver with a stronger output lets Rp go lower; the ceiling does not change.
Rise time is 30 % to 70 % of V_DD, as the standard defines it — not 10 % to 90 %.
One pull-up per line; SDA and SCL each need their own resistor.
A 5 V-tolerant part on a 3.3 V bus still uses the 3.3 V rail for this calculation.

What sets the I²C pull-up window

An I²C line is open-drain. Nothing drives it high; the pull-up does, through whatever capacitance hangs on the line. That gives the resistor a floor and a ceiling, and the tool reports both.

The floor comes from the low level. When a device pulls the line down it has to sink the pull-up current and still hold the line at or below V_OL. NXP UM10204 section 6.1 (Table 10) rates the driver at 3 mA for Standard- and Fast-mode, 20 mA for Fast-mode Plus, with V_OL = 0.4 V. Go below R_min and the low level creeps up towards the input threshold.

The ceiling comes from the rise time. UM10204 Table 11 limits t_r to 1000 ns, 300 ns and 120 ns for the three modes, and defines it between 30 % and 70 % of V_DD, not 10 % to 90 %. For an RC edge, the time between those two points is ln(0.7/0.3) = 0.8473 time constants. That constant is the whole difference between this calculator and one that multiplies by 2.2.

Both bounds, the rise time of a resistor you have already chosen, and the current and power a held-low line costs are all under How this is calculated above. SDA and SCL each need their own pull-up, so the bus pays that power twice.

Bus capacitance C_b is the total on one line: every device pin, the MCU pin, the pads and the copper. UM10204 caps it at 400 pF (550 pF for FM+). If you have not measured it, budget 10 pF per device pin (the specification's own allowance, section 6.1) plus roughly 1 pF per centimetre of trace over a ground plane. The tool builds C_b from those two terms so the estimate is at least visible.

The same formulas, with the same constants, appear in TI SLVA689, I²C Bus Pullup Resistor Calculation, section 2 and 3. The source is NXP UM10204, I²C-bus specification and user manual, section 7.1.

I2C pull-up resistor chart

The window for the common cases, computed by the calculator above from UM10204's limits: 3 mA of sink current in Standard and Fast mode, 20 mA in Fast-mode Plus, V_OL of 0.4 V, and the rise-time limit of each mode against the bus capacitance. R_min depends on the supply; R_max does not. The last two columns are the E24 value nearest the geometric middle of the window, which is the default worth reaching for when nothing else decides it.

Mode	Bus C	R_min 3.3 V	R_min 5 V	R_max	Middle, 3.3 V	Middle, 5 V
Standard-mode, 100 kHz	50 pF	967 Ω	1.53 kΩ	23.6 kΩ	4.7 kΩ	6.2 kΩ
Standard-mode, 100 kHz	100 pF	967 Ω	1.53 kΩ	11.8 kΩ	3.3 kΩ	4.3 kΩ
Standard-mode, 100 kHz	200 pF	967 Ω	1.53 kΩ	5.90 kΩ	2.4 kΩ	3 kΩ
Standard-mode, 100 kHz	400 pF	967 Ω	1.53 kΩ	2.95 kΩ	1.6 kΩ	2.2 kΩ
Fast-mode, 400 kHz	50 pF	967 Ω	1.53 kΩ	7.08 kΩ	2.7 kΩ	3.3 kΩ
Fast-mode, 400 kHz	100 pF	967 Ω	1.53 kΩ	3.54 kΩ	1.8 kΩ	2.4 kΩ
Fast-mode, 400 kHz	200 pF	967 Ω	1.53 kΩ	1.77 kΩ	1.3 kΩ	1.6 kΩ
Fast-mode, 400 kHz	400 pF	967 Ω	1.53 kΩ	885 Ω	no window	no window
Fast-mode Plus, 1 MHz	50 pF	145 Ω	230 Ω	2.83 kΩ	620 Ω	820 Ω
Fast-mode Plus, 1 MHz	100 pF	145 Ω	230 Ω	1.42 kΩ	470 Ω	560 Ω
Fast-mode Plus, 1 MHz	200 pF	145 Ω	230 Ω	708 Ω	330 Ω	390 Ω
Fast-mode Plus, 1 MHz	400 pF	145 Ω	230 Ω	354 Ω	220 Ω	300 Ω

Two things the chart makes plain. A Fast-mode bus at the specification's own 400 pF limit has no window at either supply: the rise time demands under 885 Ω, and the 3 mA sink current forbids anything under 967 Ω at 3.3 V or 1.53 kΩ at 5 V. The fixes are the ones listed further down, a buffer, Standard-mode, or a different bus. And Fast-mode Plus is not Fast-mode with a faster clock: its 20 mA sink is what makes a 400 pF bus possible, at the price of pull-ups in the hundreds of ohms.

Worked example: 3.3 V Fast-mode with 90 pF of bus capacitance

Fast-mode at 400 kHz, 3.3 V rail. Six devices on the bus (the MCU plus five peripherals), 30 cm of total SDA copper across a small backplane.

C_b   = 6 × 10 pF + 30 cm × 1 pF/cm = 60 + 30 = 90 pF

R_min = (3.3 − 0.4) / 3 mA
      = 2.9 / 0.003
      = 967 Ω

R_max = 300 ns / (0.8473 × 90 pF)
      = 300e-9 / 76.26e-12
      = 3.93 kΩ

Geometric middle = √(967 × 3934) = 1950 Ω  →  nearest E24: 2.0 kΩ

Fit a 2.2 kΩ (what was in the reel) and check it:

t_r   = 0.8473 × 2200 × 90e-12 = 168 ns          (limit 300 ns, fine)
I_low = 2.9 / 2200              = 1.32 mA         (limit 3 mA, fine)
P     = 3.3 × 1.32 mA           = 4.35 mW per line
Both lines held low             = 8.70 mW

The calculator gives R_min 967 Ω, R_max 3.93 kΩ, suggested 2.0 kΩ, and 168 ns / 1.32 mA / 4.35 mW for the 2.2 kΩ choice. The 8.7 mW is the worst case, both lines low; average power on an idle bus is close to zero since both lines sit high.

Where the I²C pull-up model stops being valid

The model is a single RC. It is right as long as the line is electrically short, which at I²C speeds is always true on a PCB, and it is right as long as the only thing pulling up is the resistor. Three things break it:

Internal pull-ups. Many peripherals and every MCU port have optional weak pull-ups, 20 kΩ to 100 kΩ. In parallel with your 2.2 kΩ they move the number a little; left on by accident with no external resistor at all, the bus has a 50 kΩ pull-up and a rise time in the microseconds. Standard-mode may still work. Fast-mode will not.
Level shifting. A mixed 3.3 V / 5 V bus with a MOSFET shifter (NXP AN10441, or a PCA9306) is two buses. Each side gets its own pull-up to its own rail, sized for its own capacitance. The FET adds a few picofarads and a body-diode path; it does not merge the two RC problems into one. A 5 V-tolerant device on a 3.3 V bus is not a level-shifting problem at all: it is simply on the 3.3 V bus and uses 3.3 V in the formula.
Cables and long buses. Once the run goes off-board, 1 pF/cm turns into 50 to 100 pF per metre of cable and C_b blows past 400 pF fast. When R_max drops below R_min the tool says so: no resistor works. The fixes are a buffer (PCA9515 / P82B715), Standard-mode instead of Fast-mode, or a different bus.

This is why the 4.7 kΩ everyone has in the drawer fails at 400 kHz. It was a fine Standard-mode value on a short 5 V bus. On the 90 pF bus above it gives 0.8473 × 4700 × 90 pF = 358 ns, already over the 300 ns limit; at 200 pF it is 796 ns and the edges are visibly rounded on a scope. At 400 pF it is 1.59 µs, which fails even Standard-mode. Fast-mode with any real bus wants something between 1 kΩ and 2.2 kΩ. The article on sizing an I²C pull-up works that window through at 3.3 V and 200 pF, and traces where the 4.7 kΩ habit came from.

Common I²C pull-up mistakes

Sizing for the pins and forgetting the copper. A 10 cm trace is 10 pF, about one extra device. A ribbon cable to a sensor board can be the whole budget.
Using 10–90 % rise time. That is 2.2 τ, not 0.85 τ, and the ceiling comes out 2.6 times too low. Scope cursors need to be set to 30 % and 70 % of V_DD to compare against the specification.
Two boards, two pull-ups. Each board's designer fitted their own, so the bus carries both in parallel and the effective resistance halves — a value nobody chose. Whether that breaks anything depends on what was fitted, and the common case is fine: two 4.7 kΩ boards land at 2.35 kΩ, still inside the window above, while two 1 kΩ boards land at 500 Ω and the weakest driver on the bus can no longer reach V_OL. Against this example's 90 pF it takes five 4.7 kΩ pull-ups, or three 2.2 kΩ ones, to reach the floor. Count what is actually fitted across every board rather than assuming either way, and decide who owns the pull-up.
Pulling up to the wrong rail. The resistor goes to the rail of the lowest V_DD device on that segment, unless every part is documented tolerant of the higher rail.
Picking the top of the window to save power. The sink current only flows while a line is held low; on a bus that is mostly idle the saving is tiny and the marginal edge is permanent. Sit near the geometric middle.