I2C pull-up resistors: the value is a window, not a number

There is no correct I²C pull-up value to memorise, because the specification does not define one. It defines a window: a floor set by how much current an open-drain output is guaranteed to sink, and a ceiling set by how fast the resistor can drag the bus capacitance through a rising edge. Any resistor between the two works; the 4.7 kΩ that “always works” is simply a value that happens to sit inside the window on small, slow buses — and outside it on plenty of real ones.

For the common case — 3.3 V supply, Fast-mode (400 kHz), 200 pF of bus capacitance — the window runs from 967 Ω to 1.77 kΩ. Pick near the top for supply current, near the bottom for edge speed. Both limits come from two short formulas in the NXP I²C specification, UM10204, worked through with the same numbers in TI’s application note SLVA689; the rest of this article is where those formulas come from, what happens outside the window, and what to do when the window closes entirely. The I²C pull-up calculator runs the same equations interactively.

Why the lines need a resistor at all

I²C works because no device ever drives a line HIGH. UM10204 defines the bus this way:

When the bus is free, both lines are HIGH. The output stages of devices connected to the bus must have an open-drain or open-collector to perform the wired-AND function.

The wired-AND is the whole protocol: any device can pull SDA or SCL LOW at any time, and the line is HIGH only when everyone has let go. That is what makes clock stretching, multi-controller arbitration and mixed-voltage buses work — and it means each line’s only source of a rising edge is the pull-up resistor. Falling edges are driven by a transistor and are fast; rising edges are a resistor charging a capacitance, and are as slow as you let them be. Every constraint on Rp follows from that asymmetry.

The floor: the driver has to win

A pull-up fights the transistor that pulls the line LOW. Make the resistor too small and the transistor loses. TI states the failure directly:

A strong pullup (small resistor) prevents the I2C pin on an IC from being able to drive low. The VOL level that can be read as a valid logical low by the input buffers of an IC determines the minimum pullup resistance [RP(min)].

The specification guarantees exactly one operating point for the output stage: UM10204’s Table 10 rates VOL at 0.4 V maximum while sinking 3 mA, for supplies above 2 V, in Standard- and Fast-mode. (Below 2 V the limit becomes 0.2·VDD at 2 mA; Fast-mode Plus drivers are rated for 20 mA.) The resistor must therefore be large enough that, with the line held at 0.4 V, no more than the rated current flows through it:

$$R_{p(\text{min})} = \frac{V_{DD} - V_{OL(\text{max})}}{I_{OL}}$$

At 3.3 V that is (3.3 − 0.4) / 3 mA = 967 Ω; at 5 V, 1.53 kΩ. Below the floor the driver is asked for more current than it is specified to sink, VOL rises, and the LOW level starts eating into the 0.1·VDD noise margin that UM10204 requires below the 0.3·VDD input threshold. The bus does not fail cleanly — it fails on the one part with the weakest output stage, on the warm day.

The ceiling starts with what “rise time” means

When a driver releases a line, the voltage climbs as a plain RC step response — R is the pull-up, C is everything hanging on the wire. UM10204 §7.1 sets up the calculation from the input thresholds VIL = 0.3·VDD and VIH = 0.7·VDD:

$$V(t) = V_{DD}\left(1 - e^{-t/RC}\right)$$

The line stops being a valid LOW when it crosses 0.3·VDD and becomes a valid HIGH at 0.7·VDD. Solving the exponential for those two crossings gives the constants UM10204 quotes to seven digits:

$$t_1 = 0.3566749 \cdot RC \qquad t_2 = 1.2039729 \cdot RC$$

The specified rise time is the span between them — not the time to reach VDD, just the time spent crossing the forbidden zone between the thresholds:

$$t_r = t_2 - t_1 = 0.8473 \cdot R_p C_b$$

That 0.8473 is nothing more than ln(0.7/0.3), but it is the constant that converts a resistor and a capacitance into a number the specification can check. Every mode’s timing budget is stated as a maximum tr, measured 30 % to 70 %.

Rp(max): the rise-time budget divided by the capacitance

Rearranged, the same equation is the ceiling:

$$R_{p(\text{max})} = \frac{t_r}{0.8473 \cdot C_b}$$

The rise-time budgets come from UM10204’s Table 11: 1000 ns in Standard-mode, 300 ns in Fast-mode, 120 ns in Fast-mode Plus. The capacitance is not yours to choose after layout — so the ceiling is really a line with slope Cb:

This is why no single resistor value can be “the I²C pull-up”. A 4.7 kΩ pull-up on a 50 pF bus rises in 0.8473 · 4.7 kΩ · 50 pF ≈ 200 ns and meets Fast-mode with margin. The same resistor on a 400 pF bus takes 1.6 µs and misses even Standard-mode. TI puts the failure mode plainly:

If the pullup resistor value is too high, the I2C line may not rise to a logical high before it is pulled low.

There is one more, smaller ceiling worth knowing exists: each connected pin may leak up to 10 µA, and UM10204 §7.4 notes that keeping the HIGH-level noise margin of 0.2·VDD against that leakage also bounds Rp from above. On a bus with many devices it can bite before the rise time does.

The worked example: 3.3 V, 200 pF, Fast-mode

SLVA689 works exactly this case, and the numbers are worth checking by hand once so the formulas stop being abstract:

Rp(min) = (3.3 V − 0.4 V) / 3 mA      = 966.7 Ω
Rp(max) = 300 ns / (0.8473 · 200 pF)  = 1.77 kΩ

TI’s note reaches the same two values — 966.667 Ω and 1.77 kΩ — and leaves the choice inside the window to the designer. The window drawn against capacitance makes the trade visible:

Anything between the lines meets the specification. Within the window, the trade is one-dimensional:

A smaller resistor will give a higher speed because of smaller RC delay, and a larger resistor will give lower power consumption.

A 1 kΩ pull-up hugs the floor: crisp 170 ns edges, maximum noise immunity on the HIGH level, maximum supply current. A 1.5 kΩ part sits comfortably in the middle. There is no extra credit for either end — the specification is pass/fail.

The window narrows with capacitance, then closes

The floor does not move with Cb; the ceiling falls as 1/Cb. So the window is widest on a short two-device bus and narrows every time a device, a connector or a few centimetres of trace is added. Setting Rp(min) = Rp(max) gives the capacitance at which it closes:

$$C_{b(\text{close})} = \frac{t_r \cdot I_{OL}}{0.8473 \, (V_{DD} - V_{OL(\text{max})})}$$

Cb(close) = 300 ns · 3 mA / (0.8473 · 2.9 V) ≈ 366 pF

At 3.3 V, Fast-mode runs out of resistor values at about 366 pF — before the 400 pF that Table 11 allows on the bus. Past that point no resistor exists that both lets the driver reach a valid LOW in 0.4 V at 3 mA and gets the line HIGH in 300 ns. The specification anticipates exactly this pinch. Note 4 to Table 10 adds a second, stronger output rating for the full load:

In order to drive full bus load at 400 kHz, 6 mA IOL is required at 0.6 V VOL. Parts not meeting this specification can still function, but not at 400 kHz and 400 pF.

With that rating the floor at 3.3 V drops to (3.3 − 0.6) / 6 mA = 450 Ω, the ceiling at 400 pF is 300 ns / (0.8473 · 400 pF) = 885 Ω, and the window is open again — provided every driver on the bus is actually rated for 6 mA. The 3 mA at 0.4 V used throughout this article is the rating every Fast-mode part must meet, so the 366 pF limit is the one a bus of mixed parts can rely on. Standard-mode, with its 1 µs budget, closes at about 1.2 nF and so never closes inside the legal capacitance range; Fast-mode is the mode where the pinch is real.

Supply voltage moves the floor

Raising VDD raises Rp(min) — more voltage across the same resistor means more current into the same 3 mA driver — while the ceiling, which only knows tr and Cb, stays put. A 5 V bus therefore has a strictly narrower window than a 3.3 V one:

UM10204 §7.2.4 runs the worst case itself:

For example, with a supply voltage of VDD = 5 V ± 10 % and VOL(max) = 0.4 V at 3 mA, Rp(min) = (5.5 - 0.4) / 0.003 = 1.7 kΩ. As shown in Figure 42, this value of Rp limits the maximum bus capacitance to about 200 pF to meet the maximum tr requirement of 300 ns.

That 200 pF is the same number that appears in the Fast-mode chapter’s design guidance: up to 200 pF of bus load, a plain resistor is fine; from 200 pF to 400 pF, UM10204 §5.1 says the pull-up device should become a current source (3 mA max.) or a switched resistor circuit. The specification is not being conservative — it is reporting where its own two formulas collide at 5 V.

What a too-weak pull-up looks like on the wire

A pull-up above the ceiling does not make the bus slower in a graceful way. The failing edge is still an exponential; it just gets pulled LOW again before it ever reaches 0.7·VDD:

Both traces in that figure are computed from the same RC response — only the resistor differs. With Rp at 10 kΩ — 5.6 times the 1.77 kΩ ceiling — SCL tops out around 0.45·VDD: below the HIGH threshold, inside the forbidden zone, and therefore invisible to every receiver on the bus. Nothing NAKs, nothing errors; the clock simply never happens as far as the targets are concerned. On a scope the giveaway is the shark-fin: edges that are clearly exponentials which never flatten out at VDD. A bus that reads back nothing but 0xFF, or a device that never ACKs its address, is worth probing for exactly this before blaming firmware — the same triage order argued in bring-up on a board that does nothing.

Marginal cases are nastier than dead ones. An edge that barely crosses 0.7·VDD near the end of the HIGH period leaves almost none of the 0.2·VDD HIGH-level noise margin the spec budgets, so the bus works on the bench and drops bits in the field. The window exists so that the edge crosses early and cleanly.

What a too-strong pull-up costs

Inside the window, the argument for a larger value is power. Whenever any device holds a line LOW — which is most of the time on a busy bus, since SCL is LOW for roughly half of every clock and SDA for every zero bit — the pull-up conducts continuously:

I(held-low) = (3.3 V − 0.4 V) / 1 kΩ = 2.9 mA per line

Two lines near the floor of a 3.3 V window can draw close to 6 mA between them during transfers — often more than the peripherals being addressed. UM10204 makes the design consequence explicit:

Portable designs with sensitivity to supply current consumption can use a value toward the higher end of the range in order to limit IDD.

For a battery-powered design the recipe is: compute the window, then take the largest standard value that still fits under the ceiling with some margin. For a design with a noisy supply and no power budget, take the smallest value above the floor. The window does not say which end to sit at; the rest of the design does.

Two boards, two pull-ups: the resistors add in parallel

The most common way a bus ends up outside its window is that nobody chose the resistor at all. Development boards and sensor breakouts almost always arrive with pull-ups already fitted, because a board has to work on its own before it works in a system. Wire two such boards together and both pairs stay in circuit: SDA now has two resistors up to VDD, not one, and they are in parallel.

Parallel resistors do not average, they divide. n equal resistors of value Rp present Rp / n to the bus, so every board added makes the effective pull-up stronger — a decision taken by the bill of materials rather than by anyone sizing anything.

Measured against the window from the worked example above — 3.3 V, Fast-mode, 200 pF, so 967 Ω to 1.77 kΩ — stacking plays out like this:

boards      n × 4.7 kΩ                n × 2.2 kΩ
  1        4700 Ω  too weak          2200 Ω  too weak
  2        2350 Ω  too weak          1100 Ω  in window
  3        1567 Ω  in window          733 Ω  too strong
  4        1175 Ω  in window          550 Ω  too strong
  5         940 Ω  too strong         440 Ω  too strong

Two things follow, and the first is not the warning usually given.

Stacking is not automatically a fault. At 200 pF a single 4.7 kΩ is too weak to meet the Fast-mode rise time; three of them in parallel is the first combination that puts the bus inside its window at all. A stack of identical 4.7 kΩ breakouts can be the reason a bus works rather than the reason it fails, which is why “remove all but one pull-up” is bad advice offered as a rule.

What breaks is the sink limit, and it breaks abruptly. Five 4.7 kΩ pull-ups, or just three 2.2 kΩ ones, put the effective resistance below the 967 Ω floor, and every open-drain output on the bus is then asked to sink more than the 3 mA the specification guarantees it can. The symptom is not a failed transfer. It is a raised VOL: the LOW level creeps up toward the input threshold, margin disappears, and the bus fails first on whichever device has the least of it, at whatever temperature leaves it with less.

So the fix is a bill-of-materials decision rather than a calculation. Count what is actually fitted across every board on the bus, divide, and check the result against the window before assuming anything is healthy. Where that lands outside, most breakouts put their pull-ups on solder jumpers precisely so they can be taken out of circuit; remove enough of them, then size what remains with the I²C pull-up calculator against the capacitance of the whole assembled bus rather than of any one board.

Where the pull-up goes on the board

UM10204 sizes the resistor and never places it, and at I²C edge rates that omission is not an oversight. A Fast-mode rising edge is allowed up to 300 ns, and a bus that behaves as a single electrical node over that time does not care where along it the resistor sits, because the whole line settles together. Whether a particular bus qualifies is a question of edge rate against propagation delay, which the critical length calculator answers directly — and for a bus on one board at 400 kHz, the answer is not close.

What matters is the count, not the position: one pull-up per line, sized for the total capacitance of everything connected, is the arrangement both window formulas assume. Two devices each pulling up their own end of the bus is the parallel case above, however far apart they sit.

One other component does have a place, and the specification is explicit that it is optional:

Series resistors Rs are optional. They protect the I/O stages of the I²C-bus devices from high-voltage spikes on the bus lines, and minimize crosstalk and undershoot of the bus line signals.

Those belong at the device pin rather than at the pull-up, and they add to what the driver sees when it pulls the line LOW — which is why UM10204 bounds them by the voltage drop they are permitted to cause while the line is held down.

Estimating Cb before the layout exists

Both limits need Cb, which UM10204 defines as an inventory rather than a component:

The bus capacitance is the total capacitance of wire, connections and pins. This capacitance limits the maximum value of Rp due to the specified rise time.

The only per-part number the specification commits to is the pin: Table 10 allows each SDA or SCL I/O pin up to 10 pF. Eight devices on the bus is 80 pF before the first millimetre of copper is drawn, which is why device count — not trace length — is usually what pushes a board bus toward the limit. Wire, connectors and cable then stack on top; a bus that leaves the board through a connector should be assumed heavy until proven otherwise.

After the board exists, the rise-time equation runs backwards into a measurement. Probe a rising edge, read the 30 %-to-70 % time, and divide out the resistor actually fitted:

Cb = tr(measured) / (0.8473 · Rp)
   = 250 ns measured with 1.5 kΩ fitted  →  ≈ 197 pF

That number feeds straight back into the window formulas, and is a far better input to the next revision than any estimate.

Standard, Fast and Fast-mode Plus side by side

All the mode dependence enters through three numbers in UM10204’s Tables 10 and 11:

	Standard-mode	Fast-mode	Fast-mode Plus
fSCL max	100 kHz	400 kHz	1000 kHz
tr max (30 % → 70 %)	1000 ns	300 ns	120 ns
Cb max per line	400 pF	400 pF	550 pF
IOL at VOL = 0.4 V	3 mA	3 mA	20 mA

The pattern worth noticing: Fast-mode Plus tightens the rise budget by 2.5× and raises the guaranteed sink current by nearly 7×. The stronger driver is what makes the tighter budget usable — at 3.3 V the Fm+ floor drops to 2.9 V / 20 mA = 145 Ω, so even at its full 550 pF the window (145 Ω to about 258 Ω) is still open. A faster mode without a stronger driver would just close the window sooner, which is exactly what happens when Fast-mode timing is attempted on a heavy 5 V bus. (Fast-mode also specifies a minimum rise time, 20 ns — edges can be too sharp for the bus’s EMC as well as too slow for its timing.)

One practical footnote from UM10204 §7.3: series protection resistors in the SDA/SCL lines (300 Ω is the manual’s example) are legitimate, but their resistance must be added into the Rp and capacitance calculations — they are inside the RC being computed, not beside it.

When the window closes anyway

Sometimes the honest calculation says no resistor exists: too many devices, too much cable, too fast a mode. UM10204 §7.2 lists four ways out, in roughly ascending order of hardware:

• Slow down. A lower fSCL relaxes nothing about tr directly, but a longer clock period tolerates a longer real rise; §7.2.1 shows how to compute the resulting maximum frequency from the actual tr and tf. Its remark that “Very long buses must also account for time of flight of signals” is the point where a bus stops being a lumped RC at all and starts behaving like the transmission lines in reflections you can see.
• Reduce Cb. Fewer devices per segment, shorter routes, no off-board stubs. Every picofarad removed raises the ceiling.
• Drive harder. Fast-mode Plus parts sink 20 mA, which lowers the floor enough to permit the small resistors a big capacitance demands. This is the fix that needs no topology change — if every device on the bus supports it.
• Split the bus. A buffer divides the capacitance into segments, each with its own pull-ups and its own full budget. UM10204 is careful about the price:

Keep in mind that adding a buffer always adds delays — a buffer delay plus an additional transition time to each edge, which reduces the maximum operating frequency and may also introduce special VIL and VOL considerations.

Beyond these, §7.2.4 describes the switched pull-up circuit — a second, lower resistance switched in only during edges — and §5.1 allows an active current source above 200 pF. Both are ways of getting a strong pull-up during the rise without paying its DC cost during the LOW; the resistor window is the simple special case where one value has to do both jobs.

The procedure

1. Estimate Cb: count pins at up to 10 pF each, add an allowance for trace and cable, or measure a rising edge on existing hardware and divide by 0.8473·Rp.
2. Compute the floor: Rp(min) = (VDD − 0.4 V) / 3 mA (20 mA for a pure Fm+ bus).
3. Compute the ceiling: Rp(max) = tr / (0.8473 · Cb) with the mode’s rise budget.
4. Check the window is open. If it is closed, no resistor fixes it — reduce Cb, drive harder, split the bus, or slow down.
5. Pick inside the window: toward Rp(max) for supply current, toward Rp(min) for edge rate and noise margin, and the nearest E24 value is fine — the window is wide wherever the design is healthy.

The I²C pull-up calculator does steps 2–4 from VDD, Cb and the mode, and shows the window it derives.

Sources

• NXP UM10204 — I²C-bus specification and user manual (Rev. 7.0) — the open-drain bus definition (§3.1.1), the electrical tables behind every number here (Tables 10 and 11, pp. 43–44), the pull-up sizing derivation with the 0.3566749/1.2039729/0.8473 constants (§7.1, p. 50), and the over-capacitance strategies, switched pull-up and series-resistor rules (§7.2–7.3, pp. 51–53).
• TI SLVA689 — I2C Bus Pullup Resistor Calculation — the same two equations stated as a design procedure, the speed-versus-power trade-off, and the worked 3.3 V / 200 pF / Fast-mode example (966.667 Ω to 1.77 kΩ) checked against in this article.

Updates

• 2026-09-13 — Fig 4’s caption called a 4.7 kΩ pull-up “marginal for Standard-mode at 400 pF”; at 400 pF it rises in about 1.6 µs and misses Standard-mode outright. The marginal case is 200 pF (≈ 800 ns). Caption corrected.
• 2026-09-13 — The section on the window closing now quotes note 4 to UM10204’s Table 10, which anticipates the 366 pF pinch by requiring 6 mA at 0.6 V for a full Fast-mode load; the earlier text read as though the specification’s own limits contradicted each other.
• 2026-09-13 — Fig 7’s weak pull-up is 10 kΩ, 5.6 times the 1.77 kΩ ceiling, not five times as the text and legend said. Fig 2 redrawn to clear a label struck through by the 5 V curve.