MOSFET gate resistor: what value, and what it actually sets

A gate resistor sets how fast the drain switches, and it does it through one capacitor. During the Miller plateau the gate voltage stops rising and every milliamp the driver can supply is discharging C_GD, so the drain slews at that current over that capacitance. Pick the edge you want and the resistor follows:

$R_{GATE} = \frac{V_{DRV} - V_{GS,Miller}}{\dfrac{dv}{dt} \cdot C_{GD}} - R_{HI} - R_{G,I}$

For the IRFP350 in TI’s active-clamp design — 15 V drive, a 20 Ω driver, 1.2 Ω of gate mesh, 148 pF of gate-drain capacitance — a 2.3 kV/µs edge needs 10.5 Ω. That is the answer to “what value”, and the gate resistor calculator gives it for any driver and FET. The rest of this article is what the resistor costs, which the datasheet does not say and the value alone does not show: the same 10.5 Ω lowers the dv/dt the FET can survive while it is held off from 1.93 kV/µs to 1.0, and that is why the same design adds a second circuit to protect the turn-off. Every figure here is from TI’s SLUA618, Balogh’s gate-drive paper, and its numerical appendices in SLUP170.

What the gate resistor actually controls

A MOSFET switches as fast as the voltages across its three parasitic capacitors can be changed. SLUA618 puts the gap plainly: practical switching times of “approximately 10 ns to 60 ns” against a theoretical “approximately 50 ps to 200 ps”, and the difference is entirely how quickly the gate driver can move charge into and out of C_GS and C_GD.

Of the two, C_GD is the one that matters for the edge, because it sits between the gate and the drain and the drain is what is moving. While the drain voltage falls, the gate-to-source voltage holds still at the Miller plateau, and the paper describes what the driver is doing in that moment:

All the gate current available from the driver is diverted to discharge the CGD capacitor to facilitate the rapid voltage change across the drain-to-source terminals.

So the drain dv/dt is simply I_G / C_GD, and I_G is the drive voltage’s headroom above the plateau divided by everything resistive in the loop — the driver’s output, the resistor fitted, and the gate mesh inside the die. The resistor is the only one of the three a designer chooses, which is why it is the knob.

The four intervals of a turn-on, with numbers

SLUA618 divides turn-on into four intervals, and SLUP170 Appendix A gives an IRFP450 with every parameter needed to put times on them: V_TH 3.51 V and a Miller plateau of 4.76 V at 100 °C, C_ISS 2600 pF, C_GD 174 pF averaged over the 380 V swing, R_G,I 1.6 Ω, driven at 13 V through 5 Ω of driver and 5 Ω of gate resistor.

1. Turn-on delay, 0 V to V_TH. The driver charges C_ISS through 11.6 Ω; nothing happens at the drain. An RC time constant of 30 ns reaches 3.51 V in about 9.5 ns.
2. Current rise, V_TH to the plateau. The FET is in its linear region and the drain current climbs to the load current; the drain voltage has not moved yet. At the paper’s average gate current for this interval, 0.76 A, it takes about 4 ns.
3. The Miller plateau. The gate holds at 4.76 V while the drain falls through 380 V. Gate current is (13 − 4.76) / 11.6 Ω = 0.71 A, all of it into C_GD: 174 pF × 380 V / 0.71 A ≈ 93 ns. This is the interval, and the only interval, the gate resistor sets.
4. Overdrive, plateau to V_DRV. The gate charges the rest of the way, R_DS(on) falls to its final value, and the drain voltage drops the last few hundred millivolts.

The plateau is where the switching loss happens — high current and high voltage in the device at once — and it is an order of magnitude longer than anything else in the sequence. Slowing it down with a bigger resistor costs loss in proportion; speeding it up with a smaller one raises the dv/dt, and the two things dv/dt breaks are next.

Solving for the edge you want

SLUP170 Appendix F designs a low-side and a high-side gate drive for an active-clamp flyback and chooses the target this way:

For this design the turn-on dv/dt of both transistors is limited below 2.3kV/µs. This value was selected to be half of the resonant dv/dt calculated before under full load conditions.

The resonant inductor slews the switching node at 2.7 A into 586 pF, 4.6 kV/µs; the FETs are made to turn on at half that. For Q1, the IRFP350:

bare driver   dv/dt = (15 − 4.2) / ((20 + 1.2) × 148 pF)           = 3.44 kV/µs
for 2.3 kV/µs R_GATE = (15 − 4.2) / (2.3 kV/µs × 148 pF) − 20 − 1.2 = 10.5 Ω
              I_G    = 10.8 V / 31.7 Ω                              = 341 mA
              t_3    = 285 V / 2.3 kV/µs                            = 124 ns

For Q2, the IRF740 behind a 33 Ω driver output, the same arithmetic gives 27.8 Ω, which the document prints as 27 Ω after rounding its gate resistance to 1.6 Ω in that line. Both are the numbers the calculator reproduces.

Two things in that block are worth reading twice. The driver’s 20 Ω is already two-thirds of the loop: a driver’s output resistance is not a detail to be added later but the starting point the resistor is measured from. And the plateau current is 341 mA against a driver that will happily quote an amp or more of peak current. SLUA618 is direct about which number matters:

Peak current capability, which is measured at full VDRV across the driver’s output impedance, has very little relevance to the actual switching performance of the MOSFET. What really determines the switching times of the device is the gate drive current capability when the gate-to-source voltage, that is, the output of the driver is at approximately 5 V.

What the same resistor does when the FET is held off

The gate-drain capacitor does not know which way the drain is moving. When the FET is off and something else slews its drain upward — the other switch in a bridge turning on, a resonant tank — current flows through C_GD out of the gate, through the pull-down path to ground, and develops a voltage across that path. If that voltage reaches V_TH, the FET turns on while its partner is on, and the supply is shorted through both. SLUP170 Appendix A5 gives the limit directly:

$\frac{dv}{dt}\bigg|_{LIMIT} = \frac{V_{TH}}{\left(R_{G,I} + R_{GATE} + R_{LO}\right) C_{GD}}$

The gate resistor is in that denominator too. For Q1, with nothing fitted, the limit is 3.2 V / ((10 + 1.2) × 148 pF) = 1.93 kV/µs. Fit the 10.5 Ω that gave the wanted turn-on edge and the limit falls to 1.0 kV/µs — while the resonant tank is still slewing the node at 4.6. The resistor chosen for one job has made the other one worse by a factor of two, and the FET will be turned on by its own drain.

This is the trade the value alone hides. A bigger gate resistor slows the edge this FET makes and lowers the edge it can tolerate, in the same direction, from the same equation.

The other resistor: gate to source

The gate resistor is in series with the drive. The second resistor most gate circuits carry is across the gate, from gate to source, and it does a job the first one cannot. Infineon’s gate-drive note puts it in its description of the simplest drive circuit: “a resistor R_GS, in the kΩ range (typically 10 kΩ), is highly recommended between the gate and source so that the MOSFET gate will be discharged if the gate becomes disconnected from the driver circuit. Without this a MOSFET may remain on when it should be off, so that when another MOSFET in the circuit switches on, a short-circuit can occur in which a very high current causes several components to be destroyed and can also burn the PCB.” Nexperia’s AN90059 says the same from the other side of the fault: “a pull-down resistor placed between gate and source ensures that the MOSFET is in a known state (off) in the case of a fault with the gate drive circuit or when there is no power being applied to the circuit … A gate-source resistance in the kΩ range is usually suitable.”

The two situations are the ones the series resistor knows nothing about. Before the driver has a supply — during power-up, or with the controller held in reset — its output is neither high nor low, and a gate with no DC path to source is a capacitor that charges from whatever leaks into it: the driver’s output stage, the drain through C_GD as the bus comes up. A few volts is enough. And if the driver’s output ever opens — a cracked joint, a driver that has failed, a connector in a remote gate drive — the same gate floats for as long as the fault lasts. The pull-down makes both cases a defined off: the gate discharges through R_GS and C_ISS in a few time constants, tens of microseconds for 10 kΩ across a few nanofarads.

Why kΩ and not less: the pull-down sits in parallel with the driver’s output, which is ohms, so at 10 kΩ it takes under a thousandth of the drive and changes neither edge. It is also why it does not do the series resistor’s job. Take Q1’s numbers from above into the dv/dt limit with the driver absent and only the pull-down holding the gate: 3.2 V / (10 kΩ × 148 pF) is about 2 V/µs, a slew any converter exceeds by three orders of magnitude. The resistor keeps an undriven FET off against leakage and a floating gate; against a slewing drain, only the driver’s low impedance does, which is Nexperia’s own remedy for gate bounce — “by adding an external C_GS or by reducing the gate drive impedance”. The kΩ pull-down and the ohms of drive resistance are not alternatives; each covers a case the other cannot.

The same note adds the clamp that sometimes shares the pads: “one or more Zener diodes can be placed between the gate and source” to keep V_GS inside its rating, back-to-back for both polarities, with the warning that they “add some capacitance which can impact switching times for small MOSFETs. For example, Zener diode BZX84-B15 has a maximum capacitance of 75 pF” — half of Q1’s C_GD, added to a gate node that the gate resistor was sized for without it.

Why the design needs a turn-off circuit as well

Appendix F’s answer is not a compromise resistor. It is a second path:

Since the resonant dv/dt is higher than the dv/dt LIMIT calculated for both Q1 and Q2 transistors, a turn-off speed-up circuit must be used in both drive circuits.

A PNP transistor across the gate resistor pulls the gate down through nothing but the gate mesh, and the document recomputes the limit with R_GATE and R_LO gone and 0.7 V of base-emitter drop taken from the threshold: (3.2 − 0.7) V / (1.2 Ω × 148 pF) = 14 kV/µs for Q1, 24 kV/µs for Q2. Three times the resonant dv/dt, comfortably.

That separates the two jobs. The gate resistor sets the turn-on edge and is sized for it alone; the turn-off circuit protects the held-off FET and is sized for that alone. A diode across the resistor is the minimal version of the same idea — turn-on through the resistor, turn-off around it — and SLUA618 section 3.4 works through the diode, PNP, NPN and NMOS variants. Whichever is fitted, the point is that one resistor was never going to serve both edges.

The resistor does not set the drive power, only where it goes

It is natural to assume a bigger gate resistor dissipates more. It does — but the total does not change. SLUA618’s Equation 9 is the whole of gate-drive power:

$P_{GATE} = V_{DRV} \cdot Q_G \cdot f_{DRV}$

No resistance appears in it. The charge Q_G has to move onto the gate and off again every cycle, and moving it through a resistance costs the same energy however large the resistance is — as the paper says, “the power dissipation is independent of how quickly the charge is delivered through the resistors.” What the resistances decide is the split. Equation 10 divides the power between the driver’s pull-up, the driver’s pull-down, the external resistor and the gate mesh in proportion to each one’s share of the loop:

Q1 at 250 kHz   P_GATE     = 15 V × 135 nC × 250 kHz                 = 506 mW
  driver, on     ½ × 20 / (20 + 10.5 + 1.2) × 506                      = 160 mW
  driver, off    ½ × 10 / (10 + 10.5 + 1.2) × 506                      = 117 mW
  R_GATE         ½ × 10.5/31.7 × 506  +  ½ × 10.5/21.7 × 506           = 207 mW
  gate mesh      ½ × 1.2/31.7 × 506  +  ½ × 1.2/21.7 × 506             =  24 mW  (in the die)

The four shares are rounded individually, which is why they sum to 508 mW against the 506 mW total.

Appendix F does the same sum for both devices — 731 mW total, 284 mW of it in the UCC3580 — and the point of doing it is the driver’s junction temperature, not the resistor’s. Fitting a larger resistor moves heat out of a controller IC into a discrete part that is easy to cool. That is a legitimate reason to fit one even where the dv/dt arithmetic says zero.

Motor drivers and bridges: the other FET decides

In a half-bridge — a motor phase, a synchronous buck — the FET whose limit matters is not the one being sized. Each device’s turn-on edge is what the other device is subjected to while held off. So the procedure is two calculations and a comparison: the high-side resistor from its own target dv/dt, the low-side limit from its own pull-down path and C_GD, and then the first against the second. If the edge exceeds the limit, the choices are a slower edge, a turn-off circuit on the victim, or a device with a higher threshold — and with a 250 W motor stage the last is rarely free.

The “gate resistor setting for motor driving” question, then, has no standalone answer. It is the same equation with the bridge partner’s numbers in it. The calculator runs one device at a time; run it for both and read the low-side limit against the high-side edge.

The second job: damping the gate

There is one more reason for the resistor, and it is the reason a small one belongs in every gate loop regardless of the dv/dt arithmetic. SLUA618 section 2.8:

The resonant circuit is exited by the steep edges of the gate drive voltage waveform and it is the fundamental reason for the oscillatory spikes observed in most gate drive circuits. Fortunately, the otherwise very high Q resonance between CISS and LS is damped or can be damped by the series resistive components of the loop.

The source inductance — the bond wire, the trace to the common ground, a current-sense resistor’s lead — and the input capacitance form a tank. Appendix A4 measured the IRFP450 on an impedance bridge: 12.9 nH and 5.85 nF, which resonate at

$f_r = \frac{1}{2\pi\sqrt{L_S\, C_{ISS}}} = \frac{1}{2\pi\sqrt{12.9\ \text{nH} \times 5.85\ \text{nF}}} \approx 18\ \text{MHz}$

and the gate rings there on every edge unless the loop’s resistance damps it. The 1.6 Ω of gate mesh is not enough on its own. This is a separate calculation from the slew rate — critical damping of a series RLC, not a Miller-plateau current — and the snubber calculator handles the same physics for a switching node; what the gate needs is the same shape of answer on a smaller scale. The practical rule from the paper’s checklist is to look:

Always check the gate drive waveform on the final printed circuit board for excessive ringing at the gate-source terminals and at the output of the driver IC.

Where the datasheet numbers come from, and what to correct

The equation is only as good as its inputs, and three of them need correcting before use. SLUP170 Appendix A is a worked procedure for each.

The threshold is a 25 °C number at 250 µA. SLUA618 notes an “approximately –7 mV/°C temperature coefficient”, and Appendix A takes its IRFP450 values from the 150 °C transfer curve, then adds 0.35 V to move them to the 100 °C operating point. The hot threshold is the one that decides whether the held-off FET stays off, and it is always lower than the line on the datasheet.

C_GD is not the C_RSS line. The datasheet measures it at 25 V; it falls steeply with drain voltage. Appendix A1 averages it over the actual swing as 2 × C_RSS,spec × √(V_spec / V_DS,off) — 340 pF at 25 V becomes 174 pF across 380 V. Using the spec line directly would halve every dv/dt in this article.

The Miller plateau is not V_TH. It is the gate voltage at which the FET carries the load current, and Appendix A3 reads it from two points on the transfer characteristic rather than from the small-signal g_fs, because “the listed gfs is a small signal quantity”. For the IRFP450 at 5 A that is 4.41 V against a 3.16 V threshold, and the 1.25 V between them is the current-rise interval’s whole budget.

Where the model stops being valid

• The waveforms are straight lines. SLUA618 says of the switching-loss estimate that calculating it exactly “is almost impossible” once source and drain inductance are included, and offers the linear approximation as “a reasonable enough compromise”. The plateau time and the loss are comparisons between two resistor values, not numbers to size a heatsink from.
• Clamped inductive switching. The intervals assume a diode clamps the drain at V_DS,off and the load current is constant through the edge, which is how a converter’s switch works and not how a resistive load does. Datasheet switching times are taken with resistive loads, and the paper warns they are “significantly different” from what a clamped inductive circuit sees.
• A MOS driver output. R_HI and R_LO are resistances. A bipolar totem-pole output is non-linear and “the equations do not yield the correct answers” for it.
• No source inductance in the slew-rate arithmetic. It sets the ringing and lengthens the delay intervals, and it is the reason the loss estimate is only an estimate.

The procedure

1. Establish the edge the power stage wants, from EMI, from rectifier reverse-recovery, or from a resonant dv/dt as Appendix F does.
2. Correct the FET’s numbers to the operating temperature and voltage: threshold, plateau, averaged C_GD.
3. Solve for R_GATE from the driver’s output resistance, the headroom above the plateau, and C_GD.
4. Compute the held-off dv/dt limit with that resistor in the loop, and compare it against the edge the FET will actually be subjected to — the partner device’s, or the tank’s.
5. If the limit is lower than the edge, add a turn-off path around the resistor and recompute with the resistor and driver pull-down out of the loop.
6. Work out the gate-drive power and where it lands; check the driver’s junction temperature.
7. Fit the board and look at the gate waveform.

Sources

• TI, SLUA618A — Fundamentals of MOSFET and IGBT Gate Driver Circuits, L. Balogh, revised October 2018. Sections 2.3 to 2.8: the critical parameters, the four turn-on and turn-off intervals, the Miller plateau, power loss equations 9 to 14, and the source-inductance resonance.
• TI, SLUP170 — Appendices A to F, Seminar 1400 Topic 2. Appendix A: the IRFP450 parameters, capacitance averaging, threshold and plateau from the transfer curve, the measured 1.6 Ω, 12.9 nH and 5.85 nF, and the three dv/dt limits. Appendix F: the active-clamp design, the 2.3 kV/µs target, 10.5 Ω and 27 Ω, the speed-up circuit, and the 731 mW.
• Infineon, AN_2203_PL18_2204_004502 — Gate drive for power MOSFETs in switching applications, P. B. Green and L. Zheng, V1.0, April 2022. Section 4.3: the basic gate drive circuit and the R_GS “in the kΩ range (typically 10 kΩ)” recommendation, with the reason.
• Nexperia, AN90059 — Power MOSFET gate driver fundamentals, Rev. 1, April 2025. Section 6: the gate-source pull-down for a known off state, the Zener clamp and its capacitance, and gate bounce.