MOSFET gate resistor calculator

The gate resistor sets the turn-on edge: R_GATE = (V_DRV − V_GS,Miller) / (dv/dt × C_GD) − R_HI − R_G,I. For an IRFP350 on a 15 V, 20 Ω driver, a 2.3 kV/µs edge needs 10.5 Ω. The same resistor lowers the dv/dt the FET can survive while held off, from 1.93 to 1.0 kV/µs here, because the current through C_GD now has more resistance to develop a gate voltage across. Enter the driver, the FET and the edge you want; get the resistor, both dv/dt figures, the plateau time and where the drive power is dissipated.

Fig 1 — Turn-on dv/dt (bold) and the held-off dv/dt limit (thin) against R_GATE; 10.5 Ω lands the edge at 2.3 kV/µs and the limit at 1.00 kV/µs.

Target turn-on dv/dt (kV/µs)

Gate resistor (0 = solve) (Ω)

Drive amplitude (V)

Miller plateau (V)

Threshold at T_J (V)

C_GD at the switched voltage (pF)

Driver pull-up R_HI (Ω)

Driver pull-down R_LO (Ω)

Gate mesh R_G,I (Ω)

Total gate charge (nC)

Switched voltage (V)

Switching frequency (kHz)

C_ISS (0 = skip) (pF)

Drain current on the edge (A)

Gate resistor for the target: 10.5 Ω
Gate current on the plateau: 340 mA through 31.7 Ω total
Turn-on dv/dt: 2.30 kV/µs
dv/dt survived while held off: 1.00 kV/µs · 18.02 kV/µs with the driver shorted out
Plateau time, 285 V swing: 124 ns
Gate-drive power: 506 mW
Where it is dissipated: driver 276 mW · R_GATE 207 mW · gate mesh 23.6 mW

The dv/dt this FET can survive while held off is lower than the dv/dt it produces when it turns on. In a half-bridge, the other FET is subjected to this edge: check the limit against the edge it will actually see, and reach for a turn-off speed-up circuit if it is too low.

How this is calculated

Standard: TI SLUA618 (Balogh) sections 2.3–2.8; SLUP170 Appendix A and F; SLYT664

$I_G = \frac{V_{DRV} - V_{GS,Miller}}{R_{HI} + R_{GATE} + R_{G,I}}$: The gate current during the Miller plateau at turn-on — the current that actually switches the device.
$\frac{dv}{dt}\Big|_{ON} = \frac{V_{DRV} - V_{GS,Miller}}{\left(R_{HI} + R_{GATE} + R_{G,I}\right) C_{GD}}$: All of I_G is discharging C_GD while the gate voltage sits on the plateau.
$R_{GATE} = \frac{V_{DRV} - V_{GS,Miller}}{\frac{dv}{dt}\, C_{GD}} - R_{HI} - R_{G,I}$: The previous line solved for the resistor. SLUP170 Appendix F, page 2-55.
$\frac{dv}{dt}\Big|_{LIMIT} = \frac{V_{TH}}{\left(R_{LO} + R_{GATE} + R_{G,I}\right) C_{GD}}$: The drain dv/dt this FET can be subjected to while held off before the gate reaches threshold. With R_LO and R_GATE shorted out, only R_G,I remains and the limit is the device's natural one.
$t_3 = \frac{C_{GD}\, V_{DS,off}}{I_G}$: Miller plateau duration, SLUA618 Eq 12.
$t_2 = \frac{C_{ISS}\left(V_{GS,Miller} - V_{TH}\right)}{I_{G2}}, \quad I_{G2} = \frac{V_{DRV} - \tfrac{1}{2}\left(V_{GS,Miller} + V_{TH}\right)}{R_{HI} + R_{GATE} + R_{G,I}}$: The current-rise interval before the plateau, SLUA618 Eq 11–12.
$P_{GATE} = V_{DRV}\, Q_G\, f_{DRV}$: Independent of every resistance in the loop. SLUA618 Eq 9.
$P_{DRV} = \tfrac{1}{2}\left(\frac{R_{HI}}{R_{HI} + R_{GATE} + R_{G,I}} + \frac{R_{LO}}{R_{LO} + R_{GATE} + R_{G,I}}\right) V_{DRV}\, Q_G\, f_{DRV}$: The driver's share; R_GATE and R_G,I take theirs in the same proportion. SLUA618 Eq 10, SLYT664 Eq 6.
$P_{SW} \approx V_{DS,off}\, I_D\, (t_2 + t_3)\, f_{SW}$: Linear approximation, both edges, SLUA618 Eq 14 and SLYT664 Eq 4. An estimate and labelled as one.

Assumptions

Clamped inductive switching: the load current is constant through the edge and a diode clamps the drain, which is how a converter's switch actually operates. SLUA618 section 2.4.
C_GD is the average over the switched voltage, not the 25 V datasheet line; the hint on that field gives SLUP170's scaling.
V_TH and the Miller plateau are taken at the operating junction temperature. The threshold falls about 7 mV/°C.
The driver output is resistive, which holds for MOS output stages and not for bipolar totem poles.
Parasitic source and gate inductance are neglected. They set the ringing, not the slew rate, and need a separate damping calculation.
The dv/dt limit is for this device held off. The edge it is subjected to comes from another device or a resonant circuit and has to be compared against it by hand.

What sets a MOSFET's gate resistor

A gate resistor sets how fast the drain slews, and it does so through one capacitor. During the Miller plateau the gate voltage stops rising and every ampere the driver can deliver goes into discharging C_GD, so the drain falls at that current divided by that capacitance. The current is the drive headroom above the plateau, V_DRV − V_GS,Miller, over the total resistance in the gate loop: the driver's output, the resistor you fit, and the gate mesh inside the die. Choose the edge you want and the resistor falls out.

The same capacitor sets a second, opposing number. When the FET is held off and something else slews its drain — the other switch in a half bridge, a resonant tank — the current through C_GD has to leave through the pull-down path, and the voltage it develops across that path lifts the gate. If it reaches V_TH the FET turns on uninvited. The dv/dt it can survive is the threshold over the same resistance and capacitance, now with the driver's pull-down in the loop. A larger gate resistor therefore slows the edge this FET makesand lowers the edge it can tolerate. The tool reports both so the trade is visible.

Gate-drive power is separate and does not depend on the resistor at all: it is the charge moved per cycle times the drive voltage times the frequency. What the resistor changes is where that power turns into heat — a bigger resistor takes a larger share out of the driver and dissipates it in itself.

Gate resistor chart: what each value buys and costs

The same FET and driver as the worked example below, with the gate resistors a drawer holds, computed by the calculator above. The two dv/dt columns are the trade the resistor makes: the turn-on edge it allows, and the drain edge the FET can be held off against with that resistor now in the pull-down path too. The plateau time is how long the driver spends at the Miller level delivering that current.

R_GATE	Turn-on dv/dt	dv/dt held off	Plateau current	Plateau time
1 Ω	3.29 kV/µs	1.77 kV/µs	486 mA	87 ns
2.2 Ω	3.12 kV/µs	1.61 kV/µs	462 mA	91 ns
4.7 Ω	2.82 kV/µs	1.36 kV/µs	417 mA	101 ns
10 Ω	2.34 kV/µs	1.02 kV/µs	346 mA	122 ns
22 Ω	1.69 kV/µs	0.65 kV/µs	250 mA	169 ns
47 Ω	1.07 kV/µs	0.37 kV/µs	158 mA	266 ns

Read the two dv/dt columns against each other. Every ohm added to slow the turn-on edge also weakens the hold-off, because it sits in series with the driver's pull-down; past a few tens of ohms the FET is more likely to be switched on by its own drain than by the driver. That is why a separate turn-off path, a diode across the gate resistor, exists.

Worked example: the IRFP350 in TI's active-clamp design

The defaults are Q1 of SLUP170 Appendix F: an IRFP350 driven by a UCC3580-4 at 15 V and 250 kHz, switching 285 V and 2.7 A. The device parameters are the note's own, already corrected to a 100 °C junction: V_TH 3.2 V, plateau 4.2 V, C_GD 148 pF, Q_G135 nC, gate mesh 1.2 Ω, driver 20 Ω up and 10 Ω down. The design target is a 2.3 kV/µs turn-on edge — half the 4.6 kV/µs the resonant inductor imposes on the node.

with no external resistor
  dv/dt_on    = (15 − 4.2) / ((20 + 0 + 1.2) × 148 pF)   = 3.44 kV/µs
  dv/dt_limit = 3.2 / ((10 + 0 + 1.2) × 148 pF)          = 1.93 kV/µs

solve for 2.3 kV/µs
  R_GATE      = (15 − 4.2) / (2.3 kV/µs × 148 pF) − 20 − 1.2 = 10.5 Ω
  I_G         = 10.8 V / 31.7 Ω                          = 341 mA
  t_plateau   = 285 V / 2.3 kV/µs                        = 124 ns
  dv/dt_limit = 3.2 / ((10 + 10.5 + 1.2) × 148 pF)       = 0.996 kV/µs

power at 250 kHz
  P_GATE      = 15 V × 135 nC × 250 kHz                  = 506 mW
  in driver   = ½ × 20/31.7 × 506 + ½ × 10/21.7 × 506    = 276 mW
  in R_GATE   = ½ × 10.5/31.7 × 506 + ½ × 10.5/21.7 × 506 = 207 mW

The calculator gives 10.5 Ω, 2.30 kV/µs, 0.996 kV/µs and 506 mW. SLUP170 prints 10.5 Ω for the same line, and 731 mW once the high-side IRF740's 225 mW is added. Note what the resistor did to the second number: the limit fell from 1.93 to just under 1 kV/µs, while the resonant tank still slews the node at 4.6. That is why the document adds a turn-off circuit that shorts the driver's pull-down out of the loop, lifting the limit to 14 kV/µs — the resistor sets the turn-on edge and the speed-up circuit protects the turn-off, and they are chosen separately.

Where the gate resistor model stops being valid

C_GD is not a constant. The datasheet's C_RSS is measured at 25 V and falls steeply with drain voltage; the value that matters is an average over the swing. SLUP170 Appendix A1 scales it as 2 × C_RSS,spec × √(V_spec / V_DS,off), which for its IRFP450 turns 340 pF at 25 V into 174 pF averaged over 380 V. Enter that average, not the spec line.
Linear waveforms. The plateau time and the switching loss are straight-line approximations of edges that are not straight. SLUA618 says of the loss estimate that calculating it exactly "is almost impossible" once parasitic inductance is included, and offers the linear version as "a reasonable enough compromise". Treat the loss row as a comparison between two resistor values, not as a number to size a heatsink from.
Source inductance is ignored. The bond wire and the trace to the common ground form a resonant circuit with C_ISS, which is where gate ringing comes from. The gate resistor damps it — that is the second reason to fit one even when the dv/dt arithmetic says zero — but the damping value is a separate calculation from the slew rate and this tool does not attempt it.
Resistive driver outputs. R_HI and R_LO model a MOS output stage. A bipolar totem-pole driver has a non-linear output and, as SLUA618 notes, the equations "do not yield the correct answers" for it.
One FET, one edge. The limit reported is what this device tolerates. In a half bridge the edge it is subjected to is the other device's turn-on dv/dt, which may have a different resistor, driver and C_GD. Run the tool for both and compare across.

Common gate resistor mistakes

Copying a value from another design. The resistor is a function of this driver's output resistance and this FET's C_GD and plateau; 10 Ω is fast on one pair and slow on another.
Using the 25 °C threshold. It falls about 7 mV/°C, so a 3.5 V datasheet line is nearer 3 V at 100 °C, and the dv/dt limit falls with it. The hot number is the one that decides whether the FET stays off.
Sizing the driver by its peak current. Peak current is quoted at full V_DRV across the output; what switches the FET is the current available with the gate sitting at the plateau, which is the headroom above the plateau over the loop resistance. SLUA618 is blunt that peak current "has very little relevance to the actual switching performance".
Fitting one resistor and expecting it to serve both edges. It slows turn-on and weakens the hold-off together. Separate turn-on and turn-off paths — a diode across the resistor, or a PNP turn-off circuit — are the standard fix, and the reason SLUP170's example needs one.
Reading the gate-drive power as the resistor's dissipation. The power is fixed by Q_G, V_DRV and frequency; the resistor only takes its share of it. A bigger resistor moves heat out of the driver into a part that is easier to cool.
Leaving the gate with no DC path to source. The series resistor does nothing for a gate the driver is not driving — before the driver has a supply, or if its output opens. Infineon's gate-drive note: a resistor R_GS "in the kΩ range (typically 10 kΩ), is highly recommended between the gate and source so that the MOSFET gate will be discharged if the gate becomes disconnected from the driver circuit"; Nexperia's AN90059 wants the same so the FET is "in a known state (off) in the case of a fault with the gate drive circuit or when there is no power". At 10 kΩ across ohms of drive it changes neither edge, and it does not replace the driver's low impedance against dv/dt: 3.2 V across 10 kΩ and 148 pF is a limit of about 2 V/µs.