100nF

Critical length calculator

Per TI AN-807, a trace can run unterminated while its rise time is 3–4 times its one-way delay. A 1 ns edge on FR-4 microstrip allows 74.9 mm, or 56.2 mm at 4:1. The driver's edge sets the limit, not the clock frequency. Stubs off a bus get about a tenth of the edge instead.

How long a trace can run unterminated before its reflections stop hiding inside the rising edge — the one-way delay against the driver's rise time, the 3:1 and 4:1 limits that rule of thumb sets, and the bandwidth the edge actually carries.

edge in flight 224.8 mm →driverloadpast the limit3:1 limit 74.9 mm
Fig 1 — a 1 ns edge occupies 224.8 mm of line; the 3:1 limit is 74.9 mm and this line is 100.0 mm.
Termination
needed — the edge is only 2.25× the one-way delay; the rule wants 3–4×
Critical length
74.9 mm at 3:1 · 56.2 mm at 4:1
One-way delay
556 ps · tr/τ = 2.25
Edge in flight
224.8 mm of line (1.25 ns linear edge)
Propagation delay
141.2 ps/in · 5.56 ns/m · εeff 2.76
Edge bandwidth
350 MHz (0.35 / tr)

Series-terminate at the driver, parallel-terminate at the load, or shorten the run below 74.9 mm. A slower driver buys length in proportion.

How this is calculated

Standard: TI SNLA027 (AN-807) — Reflections: Computations and Waveforms; propagation delay per IPC-2141A

τ=L⋅tpd\tau = L \cdot t_{pd}
One-way delay of the line: length times propagation delay per unit length.
trτ≥3–4\frac{t_r}{\tau} \geq 3\text{–}4
AN-807’s wiring rule: reflections fold into the edge while the linear rise time is 3–4 times the one-way delay. Below 3 the line needs termination.
Lmax=tr3 tpdL_{max} = \frac{t_r}{3 \, t_{pd}}
The critical length at the permissive 3:1 end; the conservative figure divides by 4 instead.
tr=t10–900.8t_r = \frac{t_{10\text{–}90}}{0.8}
Datasheets specify 10–90 %; a linear ramp spends 80 % of its time between those points. AN-807’s TTL example rounds the same conversion up (6 ns measured, 8 ns linear).
BW=ln⁡92π t10–90≈0.35t10–90BW = \frac{\ln 9}{2\pi \, t_{10\text{–}90}} \approx \frac{0.35}{t_{10\text{–}90}}
Bandwidth of a single-pole system with this rise time: t₁₀₋₉₀ = RC·ln 9 and f₃dB = 1/(2πRC), so the 0.35 is ln 9 / 2π, derived rather than recalled.
tpd=85εeff  ps/in,εeff=0.475 εr+0.67t_{pd} = 85\sqrt{\varepsilon_{eff}} \;\text{ps/in}, \qquad \varepsilon_{eff} = 0.475\,\varepsilon_r + 0.67
IPC-2141A: the εeff fit is for surface microstrip; a buried stripline uses εeff = εr. The 85 is one inch of light-speed, 84.7 ps, as IPC-2141 prints it.

Assumptions

What sets the critical length of a trace

Every trace is a transmission line; the only question is whether the driver is fast enough to notice. An edge launched into an unterminated line reflects off the open far end and comes back. If it arrives while the output is still rising, it disappears into the edge and nobody is the wiser. If the line is long enough that the edge has finished first, the reflection lands on a settled signal — and that is ringing, undershoot, and the double-clocked counter that only fails on the long board.

TI's AN-807 turns that into the wiring rule every logic family ships with: keep the rise time between three and four times the one-way delayτ and the reflections stay inside the edge. The tool computes τ for the entered line, the ratio, and the critical length where the ratio crosses 3:1 and 4:1. The delay itself comes from the same IPC-2141A fits as the microstrip calculator, so the two pages can never quote different numbers for the same stackup.

The edge bandwidth is the other half of the same judgement: a 1 ns edge carries about 350 MHz of content regardless of the clock rate it is switching at. A 10 kHz signal with nanosecond edges rings exactly as hard as a 100 MHz one.

Critical length chart

How long a trace can be before its far end needs terminating, for the edge rates drivers actually have, computed by the calculator above on FR-4. The edge column is the length of trace the rising edge occupies in flight; the limits are that length over three and over four, the two rules of thumb the page discusses. Stripline is slower, so its limits are shorter.

10–90 % riseEdge in flight, microstripLimit at 3:1Limit at 4:1Limit at 3:1, stripline
100 ps22.5 mm7.49 mm5.62 mm5.94 mm
250 ps56.2 mm18.7 mm14.1 mm14.8 mm
500 ps112 mm37.5 mm28.1 mm29.7 mm
1.00 ns225 mm74.9 mm56.2 mm59.4 mm
2.00 ns450 mm150 mm112 mm119 mm
5.00 ns1124 mm375 mm281 mm297 mm
10.0 ns2248 mm749 mm562 mm594 mm

The rise time is the driver's, not the clock's. A 1 MHz signal from a modern buffer with a 500 ps edge sits in the 500 ps row, and 40 mm of unterminated microstrip is over the limit.

Worked example: a 1 ns edge into 100 mm of microstrip

The defaults: a 1 ns edge into 100 mm of surface microstrip on FR-4 (εr = 4.4).

ε_eff   = 0.475 × 4.4 + 0.67          = 2.76
t_pd    = 85 × √2.76                  = 141.2 ps/in  =  5.56 ns/m
t_r     = 1 ns / 0.8                  = 1.25 ns  (linear equivalent)
edge    = 1.25 ns / 5.56 ns/m         = 224.8 mm of trace in flight
L_max   = 224.8 / 3                   = 74.9 mm   (56.2 mm at 4:1)
τ       = 100 mm × 5.56 ns/m          = 0.556 ns
ratio   = 1.25 / 0.556                = 2.25   →  terminate

100 mm is past the 74.9 mm limit, so this line gets a termination — or a slower buffer, which is usually the cheaper fix.

AN-807's own example, the origin of a rule of thumb older than most readers: normal TTL rises in 6 ns (10–90 %), which the note rounds to an 8 ns linear edge. Entering 6.4 ns here reproduces it exactly:

t_r     = 6.4 ns / 0.8                = 8 ns
t_pd    = 1.7 ns/ft                   = 141.7 ps/in  (custom delay)
L_max   = 8 ns / (3 × 1.7 ns/ft)      = 1.57 ft  =  18.8 in  =  478 mm

— AN-807 calls it "approximately 18 inches", and it is where the old advice that TTL tolerates a foot and a half of wire comes from.

Where the critical length rule stops being valid

The rule assumes the reflection has somewhere sensible to fold into: one driver, one line, one receiver at the end. A net with branches is several lines meeting at an impedance discontinuity, and each branch reflects on its own schedule. Stubs are therefore held to about a tenth of the edge, not a third — the RS-485 tool applies that rule for buses.

Passing the ratio does not mean the line is clean; it means the mess is over before anyone samples. A receiver that acts on the edge itself — a clock input, an async strobe, a reset — can double-count a step that a data line would never notice. Hold those to 4:1, or terminate them regardless.

Past the limit, this tool only says that termination is needed, not which one. Series at the driver is the usual answer for point-to-point CMOS: it costs one resistor, no static current, and the matched driver absorbs the reflection when it returns. Thereflections article walks the lattice diagram that shows why.

The IPC-2141 delay fits assume a solid reference plane directly under the trace. Cross a plane split and the return current detours; the delay number survives, the signal integrity does not.

Common termination mistakes

Further reading