How to terminate a clock line: series, parallel or nothing

When a clock line needs no termination, when one series resistor at the driver is enough, and the exact networks LVDS, LVPECL and HCSL clocks need.

The decision has three outcomes, and it is a tree, not a taste. If the driver’s rise time is longer than four times the one-way delay of the trace, the line needs no termination at all — it is electrically a wire, and a resistor would only cost swing. If it fails that test and runs from one driver to one receiver at the far end, series termination wins: a single resistor at the driver, sized so R_S = Z₀ − Z_out, with no DC power. Everything else — several receivers along the line, a receiver that needs the line held at a DC bias, a line that must be clean on the very first edge at every tap — pays for parallel termination at the load, in one of its three forms, with continuous current.

For the differential clock standards the decision is already made. LVDS, LVPECL and HCSL each define the network their output stage requires; the job is to use the published one, with the published values, in the published place. The rest of this article walks the tree branch by branch, with the waveforms computed from the reflection arithmetic rather than sketched.

The rule: rise time against line delay, never clock frequency

TI states the criterion in SNLA034, the application note (AN-903) whose measured waveforms anchor everything below:

As a general rule, if the signal rise time is greater than four times the propagation delay of the cable, the cable is no longer considered a transmission line.

Rearranged into the number wanted at layout time, the longest run that can go unterminated is

L_{max} = \frac{t_r \cdot v}{4}

where v is the propagation velocity. For outer-layer microstrip in FR-4 the IPC-2141 fit that the microstrip impedance calculator uses gives 140 ps per inch at ε_r = 4.3, which is about 181 mm/ns; the calculator gives the actual figure for your stackup along with Z₀ itself, and a stripline, with the whole field inside the laminate, is slower. The full derivation of why this boundary exists, with the lattice diagram and the reflection coefficients, is in the reflections article; this one takes the boundary as given and asks what to do on the wrong side of it.

A log-log plot of maximum unterminated length against rise time. The boundary line L = rise time times velocity over four separates the region where a trace behaves as a plain wire from the region where it is a transmission line that needs termination. — Fig 1 — The decision boundary, computed from TI's four-times-rise-time criterion with v ≈ 181 mm/ns — the IPC-2141 microstrip delay for ε_r = 4.3 (140 ps per inch) that the microstrip impedance calculator uses. Above the line the trace is a transmission line and one of the schemes below is due; under it, no termination.

Note what is absent from the formula: the clock frequency. A 25 MHz clock from a modern driver with a 500 ps edge crosses into transmission-line territory at about 23 mm. The rate at which the edges repeat decides how often the ringing happens, not whether it happens.

What an unterminated clock line does

On the wrong side of the boundary, an unmatched line turns every edge into a decaying exchange of reflections between its two ends. The figure below is computed from the reflection coefficients of the classic worst case — a low impedance CMOS driver, a 50 Ω trace, a high-impedance input — the same case the lattice diagram in the reflections article steps through. Read the receiver trace carefully: a new step arrives every round trip, 2·t_pd, but the overshoot and the next peak of the same sign are 4·t_pd apart. The ring frequency of an open line from a low-impedance driver is 1/(4·t_pd) — the quarter-wave resonance — so inferring a line’s delay from a measured ring frequency has to divide by four, not by two.

Computed step response of an unterminated line at both ends. The receiver overshoots to 1.43 times the final value and rings down with a new step every round trip, twice the line delay, so that same-sign peaks recur every four line delays; the driver end shows a converging staircase instead of a ring. — Fig 2 — The unterminated case, computed from the reflection coefficients of a 20 Ω driver on a 50 Ω line into a high-impedance input: Γs = −0.43, ΓL = +1. A new step arrives every round trip, 2·t_pd, and the same-sign peaks recur every 4·t_pd — the quarter-wave resonance of an open line from a low-impedance source. The driver end never shows it.

The exchange does die out. SNLA034’s measured version of this — an RS-422 driver into a receiver’s 4 kΩ input over 100 feet of twisted pair — settles after three round trips. On a data line, that can be acceptable: keep the bit time long enough and the line quiet before the sample point, which is exactly the calculation an unterminated RS-485 bus gets away with at low baud rates.

A clock does not get that grace. Every edge is a sample point for something, and the failure mode is worse than a wrong level: SCAA080 describes the steps that line reflections leave in a rising edge, and what a receiver does with a step that lingers near its input threshold:

This low-pass filter can be optimized to avoid steps in the threshold, which could cause the receiver to oscillate or to switch several times due to noise.

Several switches on one edge, on a clock, is an extra clock. That is why the clock nets get terminated first on a board where nothing else is.

Series termination: R_S = Z₀ − Z_out, at the driver

The scheme for a point-to-point clock is one resistor in series with the driver output. SCAA080 gives the whole idea in three sentences:

Series termination is a common method to maintain the signal integrity for LVCMOS drivers, if connected to a receiver with a high-impedance input. For series termination, a series resistor, R_S, is placed close to the driver. The sum of the driver impedance Z_out and R_S should be close to the transmission line impedance Z₀.

R_S = Z_0 - Z_{out}

Series termination: a resistor placed directly at the clock driver output so that the driver impedance plus the resistor equals the line impedance. The far end stays open, so the edge doubles there. — Fig 3 — Series (source) termination. R_S sits at the driver pins so that Z_out + R_S = Z_0; the receiver end stays open on purpose, because the doubling at the open end is what restores the full swing.

The far end is deliberately left open. The mismatch there still reflects — but the reflection travels back into a matched source and stops. SNLA034, which measured this on the bench, counts exactly one reflection before steady state, against the several of the unterminated case.

The subtlety is Z_out, which is neither zero nor printed on the first page of a datasheet. SCAA080 measured it for the CDCx706/x906 clock generators at the fastest slew rate: driving a 50 Ω line at 3.3 V, the output looks like 45 Ω pulling up and 42 Ω pulling down, so the proposed R_S is just 5 Ω; on a 100 Ω line the same output measures 41 Ω and 35 Ω and wants 12 Ω. Two consequences follow. First, the pull-up and pull-down impedances differ, so one resistor is always a compromise between the two edges. Second, the value belongs to a specific driver — swap the buffer for another vendor’s part and the resistor is due for review, which SNLA034 lists as one of the scheme’s real disadvantages. And it only works at all while the output impedance stays low: SCAA080’s slew-rate-limited output modes raise Z_out above Z₀, at which point there is no positive R_S left to add and the scheme is unavailable.

The step that halves, then doubles

Series termination has a signature waveform, and reading it correctly on a scope matters more than the resistor value.

Computed waveforms on a series-terminated line at the driver, at the middle of the line, and at the receiver. The driver launches half the swing and fills in one round trip later; the open receiver end sees one clean full-amplitude edge; a mid-line tap sits at half swing for a full round trip. — Fig 4 — Series termination, computed with Z_out + R_S = Z_0 (Γs = 0) and an open far end (ΓL = +1). The half step doubles at the receiver; the driver and every mid-line point wait a round trip for the fill-in — which is why series termination wants exactly one load.

The matched source launches exactly half the swing — the divider between R_S + Z_out and Z₀. That half step travels down the line, meets the open end, and doubles: the receiver sees one full-amplitude edge at t_pd and nothing afterwards. The reflection then travels home and fills the driver end in at 2·t_pd. Probed at the driver, a healthy series-terminated line shows a two-step staircase; that staircase is the scheme working, not a fault.

The same picture shows the scheme’s boundary. Any point that is not the far end sits at half swing for a full round trip — and half swing is precisely where a logic threshold lives. SNLA034 makes the consequence explicit: with a second receiver halfway along the line, the noise margin changes between the incident and reflected passes, so series termination is limited to point-to-point connections. One resistor, one load, and the load at the end of the line — all three conditions, together.

Parallel termination: match the far end instead

When the topology breaks series termination — multiple receivers, or a receiver that must see the full edge immediately — the match moves to the far end: a resistor equal to Z₀ across the line where it stops.

Parallel termination: a resistor equal to the line impedance at the far end absorbs the wave, so the receiver gets one clean edge at the line delay. The computed waveform settles immediately, but at a reduced amplitude set by the divider between driver impedance and the terminator. — Fig 5 — Parallel termination, computed with ΓL = 0. Nothing comes back, so the first edge is the final value — but the driver now works into R_T for as long as the line is driven, and the swing is the Z_0/(Z_0 + Z_out) divider, not the full rail.

With Γ_L = 0 nothing returns, so the first edge is the final value at every point on the line. SNLA034’s measured waveforms show both the driver and receiver signals free of reflections, and it credits the scheme with the note’s best numbers — operation at 10 Mb/s, and cable lengths up to 4000 feet. On the resistor value it is specific, and slightly counterintuitive:

As a general rule, however, it is usually better to select R_T such that it is slightly greater than Z_O. Over-termination tends to be more desirable than under-termination since over-termination has been observed to improve signal quality.

Up to 10 % over, per the same paragraph. The costs are the mirror image of the series case. The driver now works into R_T continuously instead of into a high-impedance input, so its power dissipation — SNLA034’s words — increases substantially, and the delivered swing drops to the Z₀/(Z₀ + Z_out) divider. Multidrop is allowed, but the stubs hanging off the line onto each receiver must stay short — under a quarter of the driver’s rise time in length — or they re-introduce the very mismatches the terminator removed.

Thevenin termination: the same match, plus a bias

A single resistor to ground terminates, but it also drags the line’s DC level to ground. Some receivers need the opposite: a line that idles at a defined voltage in the middle of their input range. SNAA377, TI’s termination guide for clock signals, covers this with the Thevenin network — a pull-up and pull-down pair whose parallel combination does the matching while their ratio sets the bias:

Z_0 = \frac{R_{TOP} \cdot R_{BOTTOM}}{R_{TOP} + R_{BOTTOM}} \qquad V_{TERM} = V_{CC} \cdot \frac{R_{BOTTOM}}{R_{TOP} + R_{BOTTOM}}

Its worked example on a 3.3 V rail uses R_TOP = 130 Ω and R_BOTTOM = 82 Ω: 50 Ω to the travelling wave, about 1.3 V to the receiver.

A Thevenin termination: 130 ohms to the 3.3 volt supply and 82 ohms to ground at the receiver. The parallel combination matches the 50 ohm line while the divider holds the input at 1.28 volts, at the cost of a constant 15.6 milliamps through the divider. — Fig 6 — SNAA377's Thevenin example. 130 Ω up and 82 Ω down look like 50 Ω to the wave and like a 1.28 V source to the receiver — and conduct 15.6 mA from rail to ground per leg whether the clock runs or not.

The bill is drawn in the figure: the divider conducts from rail to ground through 212 Ω continuously, before the driver sources a single edge — and a differential pair needs one divider per leg. SNAA377 is direct about the trade: the Thevenin termination can increase power consumption, and for power-sensitive designs it points to a Y-bias termination instead.

AC termination: parallel matching without the DC current

The remaining variant keeps the far-end resistor but breaks its DC path with a series capacitor. During an edge the capacitor is a short and the wave sees R_T = Z₀; once the line settles, the capacitor charges up and the loop current stops.

AC termination: the parallel resistor at the far end with a capacitor in series to ground, so the network matches the line during edges but blocks DC in the steady state. The capacitor is sized from the round-trip delay of the line divided by its impedance. — Fig 7 — AC termination. During an edge C_T is a short and the wave sees R_T = Z_0; at DC it is open and the loop current stops. C_T comes from SNLA034's rule — round-trip delay over Z_0 — which gives 3400 pF for its 100-foot example.

SNLA034 sizes the capacitor from the line itself — C_T at most the round-trip delay divided by Z₀ — and works the example in the figure: 100 feet of 100 Ω cable at 1.7 ns/ft gives a 340 ns round trip and a C_T of at most 3400 pF. The resulting RC constant must then stay under 10 % of the bit time, which capped that example at 300 kHz. The verdict for clocks is in the note’s own summary of the measured waveform:

There are no major reflections and driver power dissipation is reduced at the expense of a low pass filtering effect which essentially limits the application of AC termination to low speed control lines.

An RC that deliberately rounds edges is the wrong component under a continuously running clock; where it earns its place is on the slow, mostly-idle lines around the clock tree — enables, resets, control strobes — and on idle-prone differential buses, where the same trade appears in the RS-485 termination article.

The schemes side by side

SNLA034 closes with a summary table of what its bench setup — 100 feet of 100 Ω twisted pair, a 500 kHz drive — actually measured for each scheme. The panel below carries its edge-quality and data-rate columns and adds the two columns the decision usually turns on: standing power and allowed topology.

A comparison of the four single-ended schemes: unterminated is poor quality at low rates but free; series is good quality with no DC power but point-to-point only; parallel is excellent at high rates but draws continuous current; AC termination trades data rate for zero standing current. — Fig 8 — The trade, side by side. Edge quality and data rate columns are SNLA034's Table 1, measured on 100 feet of 100 Ω twisted pair; the power and topology columns are where the decision actually gets made.

Read as a tree: no termination if the rise-time rule allows it; series for point-to-point with the load at the end; parallel (or Thevenin, where a bias is needed) for everything with multiple drops or bias requirements; AC where the DC current of parallel is unaffordable and the signal is slow enough to survive the filter.

LVDS: one resistor across the pair, at the pins

The differential standards replace the tree with a prescription, because the termination is part of the output stage’s operating point. LVDS is the simplest. SNAA377:

Terminate the LVDS driver with a differential resistor (typically 100 Ω) across the output P and N signals. Place the differential resistor on the receiver side as close to the input pins as possible.

LVDS termination: a single 100 ohm resistor across the pair at the receiver input pins. The 3.5 milliamp current-mode driver develops its 350 millivolt swing across that resistor, so without it there is no signal at all. — Fig 9 — LVDS. One 100 Ω resistor across P and N, at the input pins. The driver is a 3.5 mA current source, so the resistor is not protection against reflections only — it is the component the voltage swing is built across.

The reason the resistor is non-negotiable is the driver architecture: LVDS is a 3.5 mA current-mode output, and the 350 mV swing it is specified to deliver is that current developed across the 100 Ω — no resistor, no signal, not merely a reflected one. The 1.2 V common mode comes from the driver itself, so a DC-coupled LVDS-to-LVDS clock needs nothing else. AC-coupled variants depend on the receiver: one with internal biasing and termination needs only the capacitors, while one that is biased but unterminated wants the 100 Ω moved to the driver side of the capacitors, before them, so the driver’s current always has its load.

LVPECL: the pull-downs come first

LVPECL is the standard whose termination is most often half-done, because it has two separate jobs and only one looks like termination. The output is an open emitter: without a DC path to ground it does not switch at all. SNAA377’s traditional network ties each output through R_TERM = Z₀ to a rail at V_CC − 2 V, which both terminates the 50 Ω trace and sets the roughly 15 mA output current; the output common mode sits at V_CC − 1.3 V — 2 V on a 3.3 V supply. Since a V_CC − 2 V rail rarely exists, the practical DC-coupled version is the same Thevenin pair as above — 130 Ω up, 82 Ω down per leg on 3.3 V — chosen to land the equivalent source at that voltage behind 50 Ω.

For AC-coupled LVPECL the two jobs split apart, and the order matters:

AC-coupled LVPECL termination: 150 ohm pull-down resistors at the driver give the open-emitter outputs their DC return path, series capacitors strip the DC level, and a 130 and 82 ohm Thevenin pair per leg at the receiver rebuilds a 1.3 volt bias behind a 50 ohm match. — Fig 10 — AC-coupled LVPECL, with SNAA377's values. The 150 Ω pull-downs are not termination — they are the emitter current path the open-emitter output cannot work without, and they sit before the capacitors. The Thevenin pairs re-bias the far side.

The emitter pull-downs — 140 Ω to 220 Ω, typically 150 Ω — sit on the driver side of the capacitors, because the DC return path must survive the DC break. The Thevenin pair then re-creates a bias on the receiver side. Leave out the pull-downs and the driver has no emitter current; put them after the capacitors and they do nothing.

HCSL: 50 Ω to ground on each leg

HCSL, the PCIe reference-clock standard, is another current-steering output, and its termination doubles as its load. SNAA377:

Placing a 50 Ω resistor to ground on each P and N leg sets the output swing to 750 mV and the common-mode voltage to 350 mV.

HCSL termination: an optional 33 ohm series resistor at each driver pin, then a 50 ohm resistor to ground on each leg at the driver end, with the receiver input left high impedance. The 15 milliamp current-steering output develops a 750 millivolt swing across those 50 ohm resistors, with a 350 millivolt common mode. — Fig 11 — HCSL, with SNAA377's values for a 50 Ω trace: R_S = 33 Ω completes the 17 Ω output to a source match, and the 50 Ω legs to ground — at the driver outputs, where SNAA377 puts them — give the current-steering output its DC return and turn the 15 mA into the 750 mV swing. The receiver end is left high-impedance.

That is the steered 15 mA developing across 50 Ω, and the legs sit at the driver, not the receiver: SNAA377 terminates “the HCSL driver with a 50 Ω resistor to ground on each of the P and N outputs”, and in its AC-coupled case keeps them “before the AC-coupling capacitors to provide the DC return path for the HCSL driver”. The receiver end is left high-impedance. On top of the shunt legs, HCSL commonly adds a series resistor at the driver pins — the source-match idea from earlier, applied per leg. SNAA377’s values for a 50 Ω single-ended (100 Ω differential) trace are R_O = 17 Ω and R_S = 33 Ω; for an 85 Ω differential system, 15.5 Ω and 27 Ω. Where the output impedance is not published, its advice is to fit 0 Ω first and adjust after measuring. The low-power variant LP-HCSL keeps the same 750 mV and 350 mV levels but drives them from a push-pull voltage output, so the 50 Ω legs disappear entirely and the supply current falls from roughly 15 mA to about 4 mA — the cheapest termination is the one a better output stage makes unnecessary.

Where the resistor physically goes

Every scheme above came with a place, not just a value, and the placement is enforced by the same physics as the value. A series resistor 20 mm from the driver leaves 20 mm of trace on the unmatched side of it; a parallel resistor short of the receiver leaves the last stretch as an unterminated stub. SCAA080 puts the series resistor close to the driver; SNAA377 puts the LVDS resistor as close to the input pins as possible, and the HCSL legs at the driver outputs.

Where termination resistors physically belong: the series resistor directly at the driver pins, the parallel network directly at the receiver pins, and — when a line is left unterminated — the whole run kept short, because every millimetre of trace on the wrong side of a resistor is unmatched. — Fig 12 — Placement is part of the value. R_S belongs at the driver pins and R_T at the receiver pins; any trace on the wrong side of either is an unmatched stub. With no termination at all, the whole run is the budget — about 50 mm in SCAA080's direct-drive case.

SCAA080’s unterminated case makes the placement rule quantitative. Driving 1.8 V inputs directly, its driver’s output impedance rises above 50 Ω, no positive R_S exists, and the only remaining control is distance: place the driver as close as possible to the receiver, and its simulations found a transmission line of approximately 50 mm gave good results. Where even that fails, it offers a last resort — an R_f of 200 Ω to 300 Ω at the receiver, forming a low-pass with the input capacitance that smooths the reflection steps out of the threshold region without materially slowing the edge.

The decision tree, in order

Compute L_max = t_r·v/4 with the driver’s datasheet rise time and the velocity from your stackup. Under it: route the clock and stop.
One receiver, at the end of the line? Series resistor at the driver pins, R_S = Z₀ − Z_out, using the measured output impedance, not zero. Fit the footprint even when the sums say it is marginal.
Multiple receivers, or a required input bias? Parallel at the far end — plain R_T = Z₀ to ground, or the Thevenin pair where a bias voltage is needed — and budget the standing current honestly.
A slow control line where that current hurts? AC termination, with C_T from the round-trip delay and the RC kept under a tenth of the bit.
A differential clock standard? Use its published network verbatim: 100 Ω at the LVDS input pins; pull-downs before the capacitors and a Thevenin pair after them for LVPECL; 50 Ω legs plus a 33 Ω series element for HCSL, both at the driver outputs.
Then place the parts where the scheme says — the series resistor at the driver, the parallel network at the receiver (HCSL is the exception: its legs are the driver’s load and stay at the driver), and nothing of consequence on the wrong side of either.

Sources

TI SNLA034 — AN-903 A Comparison of Differential Termination Techniques — the four-times-rise-time criterion, and the measured unterminated, series, parallel and AC waveforms with their settling behaviour, data-rate limits and summary table.
TI SNAA377 — Termination Guidelines for Differential and Single-Ended Signals — the Thevenin equations and 130 Ω/82 Ω example, and the LVDS, LVPECL, HCSL and LP-HCSL networks with their component values.
TI SCAA080 — CDCx706/x906 Termination and Signal Integrity Guidelines — measured clock-driver output impedances and proposed series resistor values, placement of the series resistor, the slew-rate limitation, and the unterminated 1.8 V case with its 50 mm result and R_f smoothing.

Updates

2026-09-13 — Fig 2 and the unterminated section corrected: the ring period of an open line driven from a low-impedance source is 4·t_pd between same-sign peaks (a new step arrives every 2·t_pd); the figure’s dimension had been drawn across one step and labelled as the period.
2026-09-13 — HCSL: the 50 Ω legs belong at the driver outputs, as SNAA377 specifies, not at the receiver. Fig 11, the HCSL section and the decision tree corrected.
2026-09-13 — The propagation velocity now matches the microstrip calculator: 181 mm/ns (IPC-2141 microstrip, ε_r = 4.3) instead of 150 mm/ns, so the worked points in Fig 1 move from 19 and 75 mm to 23 and 91 mm.