Reflections you can see: when a trace becomes a transmission line

Every trace is a transmission line. Most of the time it does not matter, and the whole skill is knowing which times those are.

The question people usually ask — how long can a trace be before it has to be treated as a transmission line — has no answer on its own, because length is only half of it. A metre of trace carrying a 1 ms edge is a wire. Ten centimetres carrying a 200 ps edge is a transmission line with a reflection problem.

The criterion

TI state it plainly in SNLA034 — AN-903, a note about terminating differential twisted-pair cable, but the rule is a statement about delay against rise time and carries over to a single-ended trace on a board unchanged:

As a general rule, if the signal rise time is greater than four times the propagation delay of the cable, the cable is no longer considered a transmission line.

So the test is

$$\begin{aligned} t_r &> 4\,t_{pd} &&\quad \text{treat it as a wire} \\ t_r &< 4\,t_{pd} &&\quad \text{treat it as a transmission line} \end{aligned}$$

where t_pd is the one-way delay along the trace. Rearranged into the form you actually want at layout time — the longest trace you can leave unterminated:

$$L_{max} = \frac{t_r \cdot v}{4}$$

Put numbers on it. The microstrip calculator uses the IPC-2141 fit for outer-layer microstrip, ε_eff = 0.475·εr + 0.67, and for εr = 4.3 FR-4 that gives 140 ps per inch — about 181 mm/ns. That is the number used below; the calculator gives the delay for your actual stackup, which is the one to use, since it varies with the dielectric constant and is slower again for a buried trace, where the whole field is in the laminate.

Rise time	L_max ≈ t_r · v / 4
10 ns (an old 74HC output)	~450 mm
2 ns (typical 74LVC)	~90 mm
500 ps (fast CMOS, DDR, LVDS)	~23 mm
200 ps (SerDes)	~9 mm

The middle row is the one that catches people. A 74LVC part driving a nine-centimetre trace is right at the boundary — and 74LVC is the jellybean logic sitting in the middle of a thousand designs whose authors have never thought about termination, because “it’s only a slow SPI bus”. The clock rate is irrelevant. A 1 MHz clock with a 2 ns edge has the same reflection behaviour as a 100 MHz clock with a 2 ns edge. The edge is the signal.

What actually happens

When a wave travelling down a line of impedance Z₀ meets an impedance Z_L, part of it continues and part comes back, in the ratio

$$\Gamma = \frac{Z_L - Z_0}{Z_L + Z_0}$$

Two limits do most of the work in practice:

• Open circuit (a CMOS input, essentially infinite impedance): Γ → +1. The wave reflects with the same polarity. The voltage at the open end briefly doubles, which is where overshoot into the protection diodes comes from.
• Short circuit: Γ → −1, inverting.

A CMOS output driving a CMOS input is the worst combination available: a low source impedance (say 20 Ω) at one end, a near-infinite one at the other. Neither end matches the 50 Ω line, so the energy bounces until resistive loss finishes it.

The lattice diagram

The classic way to see this is a lattice — or bounce — diagram, from TI’s SNLA027, which is AN-807 and still the clearest treatment of it. Distance runs across, time runs down, and each diagonal is one one-way trip.

Read it as a bookkeeping exercise. The driver launches a step whose size is set by the divider between its output impedance and the line — 50/(20+50) ≈ 0.71 of the supply, not the full swing. That partial step travels to the far end, reflects with Γ ≈ +1 (so the far end sees 2 × 0.714 ≈ 1.43, the overshoot), travels back, reflects off the source with Γ = −0.43, and so on, each round trip 43 % of the last and alternating in sign.

What you see on a scope at the receiver is the running sum: a step that overshoots to 1.43, drops to 0.82 when the first return arrives, climbs back to 1.08, and so on. Each new step lands one round trip — 2·t_pd — after the last, and alternates in sign, so the same-sign peaks are two round trips apart. AN-807 says it in one line: the oscillation period or ringing is 4τ, τ being the one-way delay. That spacing is the tell. If the ringing period is 4·t_pd — steps every 2·t_pd — it is a reflection, not oscillation, and you can read the one-way delay of the trace off the scope as a quarter of the ring period. Halve that by mistake, taking a step for a period, and the length you infer is twice what it is.

The staircase at the driver end looks completely different from the ringing at the receiver end, which is why probing at the source can convince you there is no problem.

Three ways to stop it

Series termination at the source. Put a resistor in series with the driver output, sized so R_series + Z_out ≈ Z₀ — for a 20 Ω driver on a 50 Ω line, 33 Ω, which is why 33 Ω is the value you see everywhere. The launched step is now half amplitude; it doubles at the open far end to the full swing; and the return reflection is absorbed by the matched source. Γ at the source is zero, so the bouncing stops after one round trip.

• Costs: one resistor per net, no DC power, and the receiver must be at the end of the line. It does not work for a bus with receivers tapped along the middle, because the mid-line receivers see the half-amplitude step for one round-trip time before it fills in.

Parallel termination at the load: a resistor to ground (or a Thévenin pair) equal to Z₀. Γ at the load is zero, nothing comes back, and the received edge is clean and full-amplitude immediately.

• Costs: continuous DC current whenever the line is driven, and the driver has to be able to source it into 50 Ω.

AC termination: the parallel resistor with a series capacitor, so the DC path is broken. Same trade as on an RS-485 bus — the RC slows the edge and limits the usable data rate.

For point-to-point CMOS nets on a board, series termination at the source wins almost every time: no static power, one component, and it also reduces radiated emissions by slowing the edge into the line.

What to do about it

Most boards need none of this, and the useful outcome of knowing the rule is knowing which nets to spend attention on:

1. Find the fast edges, not the fast clocks. Read the driver’s rise time from its datasheet, not from the bus speed.
2. Compute L_max = t_r · v / 4 and check it against your longest routed length for those nets. The critical length calculator does this from the rise time and the stackup, and shows the propagation delay it used rather than assuming one.
3. On the ones that fail, put a series resistor footprint at the source. Fit 0 Ω, and populate 33 Ω only if you need it. A footprint costs nothing at layout and is unobtainable afterwards.
4. Keep the return path continuous. A perfectly terminated trace crossing a split in its reference plane has an impedance discontinuity anyway, and the plane split is a far worse offender than the resistor value.

That last point matters more than the first three combined, and it is what TI’s layout guide SPRAAR7 spends its time on: route over a solid reference plane, never across a split or a void, because routing across a plane split or a void in the reference plane forces return high-frequency current to flow around the split or void — which is extra inductance, an impedance discontinuity and a radiating loop all at once. The characteristic impedance in every formula above assumes a continuous reference under the trace. Break it and none of the numbers mean anything.

Sources

• TI SNLA034 — AN-903 A Comparison of Differential Termination Techniques — the four-times-rise-time criterion and the unterminated, series, parallel and AC termination cases, written for differential twisted-pair cable.
• TI SNLA027 — AN-807 Reflections: Computations and Waveforms — the lattice-diagram method, worked for voltage-source, matched-source and current-source drivers, and the 4τ ringing period.
• TI SNAA377 — Termination Guidelines for Differential and Single-Ended Signals — choosing a scheme once the signal is differential.
• TI SPRAAR7 — High-Speed Interface Layout Guidelines — length matching and reference-plane continuity in practice.

Updates

• 2026-09-13 — Corrected the ringing-period rule. For an open line driven from a low-impedance source the load voltage steps every 2·t_pd but the same-sign peaks — one ringing period — are 4·t_pd apart, as AN-807 states; the earlier text called 2·t_pd the period, which would put an inferred trace length at double its true value. Fig 1 now prints the load voltage at each arrival and both spacings.
• 2026-09-13 — Replaced the 150 mm/ns microstrip velocity with the 181 mm/ns the site’s microstrip calculator gives for εr = 4.3 (IPC-2141, 140 ps/in), and recomputed the L_max table from it; the earlier figures were about 17 % low.
• 2026-09-13 — Corrected the title of SNLA034 — it is AN-903, a differential-cable termination note — and attributed the reference-plane rule to SPRAAR7, which is the document that states it.