ADC charge-bucket settling calculator

A SAR ADC does not politely sample a voltage; it connects a discharged capacitor to your amplifier and takes what it needs. This works out the kick that produces, how fast the R_FILT/C_FILT bucket recovers from it, and whether that lands inside half an LSB before the acquisition window closes.

Fig 1 — the 1.95 V charge-sharing step decaying toward the 152.6 µV half-LSB band; settles in 173 ns of a 300 ns window.

Resolution (bits)

Full-scale range (V)

Sampling capacitance C_SH (pF)

Bucket capacitor C_FILT (pF)

Filter resistor R_FILT (Ω)

Switch resistance R_ON (Ω)

Acquisition time (ns)

Worst-case input step (V)

Settling: settles in 173 ns — 127 ns of the window to spare
Target: 152.6 µV — half of a 305.2 µV LSB
Charge-sharing step: 1.95 V when the switch closes · 9.5 time constants to decay away
Bucket ratio: 9.3× the sampling capacitance
Time constants: 1.8 ns redistribution · 17.3 ns refill
Filter cutoff: 10.2 MHz

The bucket is only 9.3× the sampling capacitance. Below about 10× the sampling switch pulls its charge from the amplifier instead of the capacitor, which is the transient most op amps handle badly.

A first-order estimate for choosing starting values. TI SBAA286 is explicit that the final R_FILT and C_FILT come from a SPICE transient simulation of the actual amplifier and converter — this arithmetic does not model the amplifier’s own recovery.

How this is calculated

Standard: Circuit and criterion from TI SBAA286 (Driving a high-voltage SAR ADC with a buffered instrumentation amplifier); the settling arithmetic is first-order RC analysis, not a transcription — SBAA286 obtains its final values from SPICE

$\tfrac{1}{2}\,\text{LSB} = \frac{FSR}{2^{\,n+1}}$: The settling target. SBAA286 designs its 16-bit ±10 V front end to "½ of a LSB (152 µV)", which is this expression for FSR = 20 V and n = 16.
$V_{kick} = V_{step} \cdot \frac{C_{SH}}{C_{SH} + C_{FILT}}$: Charge sharing when the sampling switch closes: the two capacitors redistribute, and a finite bucket means the pin moves. This is why C_FILT is sized many times C_SH.
$\tau_{share} = R_{ON}\,\frac{C_{SH} C_{FILT}}{C_{SH} + C_{FILT}}, \qquad \tau_{refill} = R_{FILT}\,(C_{FILT} + C_{SH})$: Two phases with two different circuits: redistribution happens through the switch alone with the capacitors in series, then the driver refills both through the filter resistor.
$t_{settle} \approx 5\,\tau_{share} + \tau_{refill} \cdot \ln\!\left(\frac{V_{kick}}{\tfrac{1}{2}\text{LSB}}\right) \leq t_{acq}$: The deadline. Each extra bit of resolution adds ln 2 ≈ 0.69 time constants; the logarithm is why 16-bit settling is only about 30 % slower than 12-bit, not sixteen times.
$f_c = \frac{1}{2\pi R_{FILT} C_{FILT}}$: Cutoff of the same RC. SBAA286’s worked values (42.2 Ω, 370 pF) give the 10.2 MHz it quotes in its noise budget.

Assumptions

The amplifier is an ideal source behind R_FILT. It is not: a real driver has finite bandwidth, slew rate and output impedance, and its own recovery from the kick can dominate everything computed here.
SBAA286 states plainly that R_FILT and C_FILT are found with a SPICE transient of the actual amplifier and converter. Treat these numbers as starting values to simulate, not as a result.
Linear settling only — no slew limiting, and no amplifier instability from driving a capacitive load.
The redistribution phase is allowed five time constants; it is fast enough that the exact allowance rarely matters, and the refill term dominates.
One channel, one conversion. A multiplexer that switches channels between conversions presents the full-scale step every time, which is the default here.

What sets ADC charge-bucket settling time

The input of a SAR ADC is not a high-impedance pin. It is a capacitor on a switch, and every acquisition connects that capacitor — often holding theprevious sample, or nothing at all — to whatever is driving it. Charge redistributes in nanoseconds, the pin voltage jumps, and the driver then has until the end of the acquisition window to put it back where it belongs. Miss that deadline and the conversion happens on a voltage that is still moving: gain error and distortion that look like a bad amplifier and are actually a timing problem.

The standard fix is the charge bucket: a capacitor at the ADC pin large enough to supply the sampling charge locally, and a small series resistor isolating the amplifier from the switched load it hates. This page sizes the consequences. The kick is the capacitive divider between C_SH and C_FILT; the recovery is an exponential with τ = R_FILT(C_FILT+C_SH); the target is half an LSB, which is the criterion TI SBAA286 designs its own front end to.

One honest caveat, stated because SBAA286 states it: that note picks its R_FILT and C_FILT with a SPICE transient of the real amplifier and converter, not with a formula. What is here gets you starting values and shows which term is hurting — it does not model the amplifier's own recovery, which on a slow op amp is the whole story.

Worked example: a 16-bit SAR in a 300 ns acquisition window

The defaults are SBAA286's front end: a 16-bit ±10 V ADS8568 with 40 pF of sampling capacitance and a 50 Ω switch, behind the note's R_FLT = 42.2 Ω and C_FLT = 370 pF, sampling a full-scale step in a 300 ns window.

½ LSB    = 20 V / 2¹⁷                       = 152.6 µV   (SBAA286: "152 µV")
V_kick   = 20 V × 40 / (40 + 370)           = 1.951 V
bucket   = 370 / 40                         = 9.3 ×

τ_share  = 50 Ω × (40 ∥ 370) pF = 50 × 36.1 pF = 1.80 ns  → 5τ = 9.0 ns
τ_refill = 42.2 Ω × 410 pF                  = 17.3 ns
k        = ln(1.951 / 152.6 µ) = ln(12 788) = 9.46 τ

t_settle = 9.0 + 9.46 × 17.3                = 173 ns   of a 300 ns window
f_c      = 1 / (2π × 42.2 × 370 pF)         = 10.2 MHz  (SBAA286's figure)

Note how gently resolution bites. Going from 16 bits to 18 costs 2 × ln 2 = 1.4 more time constants — about 24 ns here — while halving C_FILT would save more than that and cost far more in kick. The logarithm is the reason high-resolution SARs are not impossibly hard to drive; the acquisition window usually is.

Where the charge-bucket model stops being valid

The model assumes an ideal voltage source behind R_FILT. A real amplifier has finite bandwidth and slew rate, and it has just been hit with a step through a capacitive load — the thing it is least good at. SBAA286 chooses a 22 MHz OPA827 buffer for exactly this and still verifies in simulation. If the driver's bandwidth is not comfortably above the filter cutoff computed here, this page is optimistic.

R_FILT is a compromise with two failure modes, and only one of them appears above. Too large and the refill never finishes, which the tool shows. Too small and the amplifier sees the raw switched capacitance, peaks, and may oscillate — which it does not show at all. Values in the tens of ohms exist because of the second problem.

Nothing here covers noise. The same RC sets the front end's bandwidth and therefore how much amplifier noise reaches the converter; SBAA286 works that budget alongside the settling one, and the two pull R and C in opposite directions.

Common ADC driver mistakes

Treating the ADC input as high impedance. It is a switched capacitor, and the datasheet's input model — C_SH, R_ON, acquisition time — is the specification the front end must meet.
Sizing C_FILT from the anti-aliasing requirement alone. It also has to be many times C_SH (about ten, as a starting point) or the sampling switch takes its charge from the amplifier.
Using an X7R for the bucket. Its capacitance moves with the voltage across it, which puts a signal-dependent error directly on the sample. C0G, as SBAA286 specifies.
Forgetting the multiplexer. A shared front end that hops channels presents a full-scale step every acquisition; a settling budget computed for a slowly varying single channel does not apply.
Believing this page over a simulation. It is a starting point by construction — TI's own note goes to SPICE, and so should the final values.