Should you split analog and digital ground planes?

One continuous ground plane with partitioned placement beats a split: where return current really flows, where AGND and DGND tie, and when a moat is right.

Almost never. The rule that survives contact with EMC testing is: one solid ground plane, components partitioned into an analog region and a digital region, and routing disciplined so that no digital trace — and therefore no digital return current — ever passes through the analog region. The isolation a moat promises is delivered by placement, and delivered better, because return current at frequency already refuses to wander: it flows in a narrow band directly under its own trace.

The split earns its place only in a narrow set of cases — TI’s worked example is a weighing scale built around a ≥20-bit delta-sigma ADC — and even then only with a single bridge that every crossing trace routes over. Cut the plane out of habit, route one trace across the moat, and the board acquires a loop antenna sized by the detour the return current is forced to take. The rest of this article is the mechanism, quoted from TI’s grounding series (SLYT499 and SLYT512) and from SNAA113, because the argument is only as good as the physics under it.

Return current does not flow where the schematic says

A schematic draws ground as a symbol. The board has to draw it as copper, and the current in that copper chooses its own path: the path of least impedance. The mistake behind most grounding folklore is assuming “least impedance” means “least resistance” at every frequency. It does not — resistance rules at DC, inductance rules everywhere interesting. SLYT499 states where the high-frequency return actually goes:

The smallest inductance path is directly next to the trace. So, regardless of the plane — power or ground — the return current flows on the plane adjacent to the trace. The current spreads out slightly in the plane but otherwise stays under the trace. The actual distribution is similar to a Gaussian curve in nature.

Top view of a ground plane with an L-shaped signal trace from a driver to a load. At DC the return current takes the straight diagonal path of least resistance; at high frequency it follows directly under the trace, because that path encloses the least loop area and therefore the least inductance. — Fig 1 — Two candidate return paths on the same plane. At DC the straight diagonal wins: least resistance. Above the crossover the path directly under the trace wins: least loop area, least inductance. The plane does not need to be told — the current finds it.

The reason is loop area. The inductance of a current path is set by the area the outgoing current and its return enclose between them; the return that minimises inductance is the one that shadows the trace. This is the same fact that makes the plane under a microstrip half of the transmission line — the microstrip impedance calculator is computing the geometry of exactly this trace-and-return pair.

How tightly the return hugs the trace

SLYT499 gives the distribution of return current in the plane as a function of distance D from a trace at height h above it:

i(D) \;=\; \frac{I_O}{\pi h}\,\cdot\,\frac{1}{1+\left(\dfrac{D}{h}\right)^{2}}

with I_O the total signal current in amperes and i(D) the plane current density in A/cm. Integrating that curve says half of the return current flows within one trace-height either side of the trace, and roughly 80% within three. On a 0.2 mm prepreg, “the return path” is a band about a millimetre wide.

Return current density in a ground plane versus distance from the signal trace: the density falls as 1 over 1 plus (D over h) squared, so half of the return current flows within one trace-height either side of the trace, and about 80 percent within three. — Fig 2 — The return-current distribution from SLYT499: i(D) = I₀ / (π·h·(1+(D/h)²)). Integrating it, half the return current flows within ±h of the trace and ~80% within ±3h — the return is not "somewhere in the plane", it is a shadow of the trace.

SLYT499 draws the conclusion that matters for the split-plane question: digital ground currents resist flowing through the analog portion of a shared plane, and so do not corrupt the analog signal — provided the digital traces themselves stay out of the analog portion. The isolation everyone wants from the moat is already present in an uncut plane. SNAA113 calls the same mechanism the proximity effect: outgoing and return currents pull toward each other to minimise the energy in the magnetic field between them.

Where the crossover sits

How high is “at frequency”? SNAA113 is specific:

Once the frequency reaches a few MHz, however, the path of least impedance becomes the path of least inductance.

The impedance of any candidate return path is

|Z| \;=\; \sqrt{R^{2} + \left(2\pi f L\right)^{2}}

and the two terms change hands early. Figure 3 evaluates that relation for two representative loops — a straight-line detour with low resistance but 50 nH of loop inductance, against the under-trace shadow with six times the resistance but a tenth the inductance. The curves cross below 10 kHz; by SNAA113’s few-megahertz mark the resistive term is irrelevant for either path, and loop area decides everything. Every harmonic of a logic edge lives far above the crossover.

Log-log plot of return-path impedance versus frequency for two paths: a straight detour with low resistance but high inductance, and the under-trace path with more resistance but far less inductance. The curves cross in the kilohertz region; above it the low-inductance path is the path of least impedance. — Fig 3 — |Z| = √(R² + (2πfL)²) for two representative return loops. The straight detour (0.5 mΩ, 50 nH) beats the under-trace path (3 mΩ, 5 nH) only at the bottom of the plot; by a few megahertz — SNAA113’s threshold — impedance is essentially all inductance, and loop area decides everything.

Skin effect pushes in the same direction: at frequency, current abandons the interior of a conductor for its surface, so surface area matters more than cross-section. SNAA113 works the numbers — at 40 MHz a 0.006 in × 0.0015 in trace has an AC resistance of 0.11 Ω per inch, doubling its thickness recovers only 17%, while doubling its width recovers 44%. A plane, all surface, is the best conductor the board can offer — which is one more reason to leave it whole.

What a moat does to a return path

Now cut the plane, and route one trace across the cut. The signal crosses on the trace; the return cannot. It has to travel to wherever the two planes join — often a single tie — and back, and everything between the trace and that detour is enclosed loop area. SLYT512, which opens with exactly this picture:

High-frequency currents flowing in large loops produce radiation and high ground inductance. Low-level analog currents flowing in large loops are susceptible to interference.

A trace crossing the moat between split analog and digital ground planes. The return current cannot follow under the trace; it detours all the way around the moat to the single tie point, and the area between trace and return becomes a loop antenna. — Fig 4 — A trace routed across a split. The return current cannot cross the moat, so it detours to the single tie — and everything between the trace and its return is enclosed loop area: radiation going out, susceptibility coming in.

The loop radiates on the way out and receives on the way in — the antenna works in both directions. SNAA113 states the scaling: radiation increases with loop area because of the field fringing around the conductors, and the loop the moat creates is as large as the detour it forces. SLYT499 adds the test-lab evidence:

During EMC tests, most problems are observed when traces are routed across a slot or a split in a ground or power plane. Since this routing causes both radiation and crosstalk issues, it is not recommended.

The same failure happens in miniature at a via field whose clearance holes merge into an unintended slot: the return reroutes around the obstacle, its field starts overlapping other traces (crosstalk), and the trace impedance over the gap is disturbed — the discontinuities that reflections you can see puts on a scope.

The worst version: planes tied only at the power supply

A common variant ties the analog and digital planes together only at the supply connector, on the theory that noise “drains” there. SLYT512:

If the two planes are connected only at the power supply […], the return current is forced to flow all the way back to the power-supply ground, which is a really big loop! Also, the analog and digital ground planes, which are at different RF potentials and connected with long wires, unfortunately form a very effective dipole antenna.

Split ground planes whose only connection is back at the power supply. A trace crossing between them forces its return current up one long supply wire and down the other, and the two planes at different RF potentials driven through long wires behave as a dipole antenna. — Fig 5 — Split planes joined only at the supply. The return loop now includes both supply leads, and the two planes sit at different RF potentials on the ends of long wires — SLYT512 calls the result a very effective dipole antenna.

That sentence contains both EMC principles SLYT499 lays down for grounding: currents should be returned to their sources locally and as compactly as possible, or a loop antenna results; and a system should have only one reference plane, because two references form a dipole. A split plane violates the first the moment routing slips, and the second by construction.

The modern rule: one plane, partitioned placement

SLYT512’s recommendation, stated as directly as an application note ever states anything:

It is always preferable to use only one ground plane, partitioning the PCB into analog and digital sections […]. Analog signals must be routed only in the board’s analog section, and digital signals must be routed only in the board’s digital section, with both on all layers. Under these conditions, the digital return currents do not flow in the analog section of the ground plane and remain under the digital signal trace.

Two layouts compared. Left: split analog and digital planes separated by a moat, where any trace crossing the moat loses its return path. Right: one continuous plane with the components partitioned into an analog region and a digital region and the converter placed across the boundary — the layout SLYT512 recommends. — Fig 6 — The usual way and the right way. A split isolates by cutting copper and creates an antenna the moment routing slips. A partition isolates by placement: one plane, analog components in one region, digital in the other, the converter on the boundary — and the return currents never mix by themselves.

Partitioning gets the isolation the moat was supposed to buy, without cutting the return path of anything. The digital return currents stay in the digital region because the physics of Figure 2 keeps them there; the analog region sees none of them because no digital trace crosses it. The boundary is a placement decision, drawn once at floorplanning time: converters and other mixed-signal parts sit on the line, analog signal conditioning on one side, buses and logic on the other.

Partitioning is routing discipline, not copper artwork

The one way partitioning fails is the one way it can: a trace routed on the wrong side of the line. SLYT512’s summary is three clauses long, and the third is the one that gets broken:

So for any PCB layout, the important points are to use a single ground plane, partition it into analog and digital sections, and apply discipline in routing.

One partitioned ground plane where a digital trace has been routed through the analog section. Its return current follows underneath it, sweeping digital switching current through the quiet analog region — the failure that makes partitioning look broken when it is really a routing error. — Fig 7 — How partitioning fails: not by physics but by routing. A digital trace that wanders across the boundary drags its return current — that narrow shadow from Fig 2 — straight through the analog section. SLYT512’s one warning about the method.

A digital trace that wanders through the analog section drags its return — that narrow shadow — straight through the quiet region, and the result looks exactly like “partitioning doesn’t work”. It is not the plane that failed. Keep-out regions in the CAD tool make the discipline mechanical rather than heroic: define the analog region, forbid digital nets inside it, and the autorouter cannot commit the error either.

What AGND and DGND actually name

The pins are the source of most of the confusion, and SLYT499 addresses it head on:

Note that the pin names, AGND and DGND, refer to what’s going on inside the component and do not necessarily imply what one should do with the grounds externally.

Inside the package, the converter’s analog and digital sections have separate ground networks so that fast digital current does not flow through the analog ground bonds. Each network reaches its pin through unavoidable bond and lead inductance, and the digital side’s switching current develops a voltage across that inductance:

V \;=\; L\,\frac{di}{dt}

which couples into the analog section through stray capacitance. The IC designer already paid for the separation; nothing done outside the package can improve on it.

Inside a data converter: separate analog and digital sections joined by stray capacitance, each reaching its AGND or DGND pin through bond and lead inductance. Fast digital current through that inductance generates V equals L di/dt, which couples into the analog section — the reason both pins tie to the same plane at the device. — Fig 8 — What AGND and DGND actually name: the two internal grounds, kept apart inside the package so digital di/dt through the bond inductance stays out of the analog section. Outside, both tie to the same low-impedance plane with minimum lead length — extra impedance in the DGND leg makes the internal coupling worse, not better.

What the board can do is avoid making it worse. SLYT499’s instruction is to join AGND and DGND externally to the same low-impedance ground plane with minimum lead lengths — any extra impedance in the DGND connection raises the digital-side bounce and couples more noise into the analog section, not less. And if the planes are split anyway, the choice of which plane gets the pins is not a coin toss:

Remember that a data converter is analog!

Both pins go to the analog plane. Tied to the digital plane instead, the digital plane’s noise appears in series with a single-ended analog input referenced to the analog plane — summed straight into the signal. The cost of putting both pins on the analog side is a small digital current injected into the quiet plane, which SLYT499 says to minimise by keeping the converter’s output fan-out low.

Low digital currents, high digital currents

That small-current assumption deserves a check. A flash-style converter draws little digital current, and the local decoupling capacitor from V_Dig to DGND closes the transient loop before it touches the plane. But converters have grown digital: SLYT499 notes that a sigma-delta ADC carries a complex digital filter that adds considerably to the digital current in the device. When those currents are large — or have DC and low-frequency components a reasonable capacitor cannot supply — the leftover current must flow somewhere, and on a single-plane board it flows through the plane.

For that case SLYT499 offers the exception to its own rule: connect AGND to the analog plane and DGND to the digital plane, accepting that the noise between the two planes now appears directly between the converter’s ground pins. The margin has to be watched, and the note suggests protecting the part: back-to-back Schottky diodes across the planes keep the difference under 0.3 V — beyond which the IC can be damaged, because the difference sits directly across AGND and DGND. A ferrite bead is the alternative tie: DC-connected, isolating above a few megahertz where the bead becomes resistive, at the price of possible DC ground loops in high-resolution systems. SLYT499’s practical advice is to fit jumpers or straps so both schemes can be tried on the real board.

The star point at the converter

Datasheets usually show the split-plane version with the planes joined at the converter, and there is a reason the recommendation persists: it puts the system’s star ground at the mixed-signal device. A star ground means every voltage in the circuit is measured with respect to one defined point — not, as SLYT499 puts it, to an undefined ground wherever one can clip a probe. SLYT512 places it precisely:

System star ground connections should be right below each mixed-signal device with minimal trace lengths and no vias.

A mixed-signal converter with its AGND and DGND pins joined and tied to the ground plane at one point directly below the package — the system star point — while a local decoupling capacitor from VDig back to DGND keeps the digital transient loop small and local. — Fig 9 — The star point, done where it belongs: AGND and DGND joined and taken to the plane right below the device, minimal length, no vias. The local capacitor from V_Dig to DGND closes the digital transient loop before it ever reaches the plane.

On a single-plane board the star point costs nothing: AGND and DGND join and drop to the plane directly under the package. The local V_Dig decoupling capacitor belongs in the same picture, and its loop is subject to the same geometry as every decoupling loop — the via is the decoupling is about keeping exactly this loop small.

When a split is genuinely right

Rarely — and deliberately. SLYT512’s example is the high-resolution, low-speed corner: a weighing scale built on a ≥20-bit delta-sigma ADC, where microvolt-level DC accuracy outranks radiated emissions. If the split is truly necessary and traces must cross, the planes join at one bridge first, and every crossing trace routes over that bridge, so each return still flows directly underneath its own trace with a small loop.

The one defensible split: two planes joined by a single bridge, with every trace that must cross the split routed over that bridge, so each return current still flows directly underneath its trace through the bridge copper. — Fig 10 — If a split is genuinely necessary, the planes join at one bridge and every crossing trace routes over it. Each return still travels directly under its trace, so the loop stays small. SLYT512’s example: weighing scales with ≥20-bit delta-sigma ADCs.

Signals that cannot share the bridge cross the split without needing a ground return at all: optoisolators (light), transformers (magnetic field), or a true differential pair, where the signal flows down one trace and back on the other. Everything else stays on its own side. A split without a bridge, or with traces crossing away from it, is not a grounding strategy — it is Figure 4 waiting to be measured.

A pour is not a plane

Flood-filling every spare patch of the signal layers with grounded copper feels like more of a good thing. SNAA113 disagrees:

An area of copper, or other board plating metal, that is grounded at one point can also form an antenna that will radiate energy that is in the ground plane at that point.

A copper pour grounded by a single via at one end. The far end is driven by whatever noise exists on the plane at the tie point and radiates it — the reason SNAA113 says to stitch the far end with a second via or delete the pour entirely. — Fig 11 — A pour is not a plane. Grounded at one point, the strip is an antenna fed by whatever noise sits on the plane at that point. SNAA113: ground the other end too, or leave the copper out.

A plane earns its properties by carrying return current in a closed, tight loop. A pour tied at a single point carries no return current — it is a conductor with one end driven by whatever noise sits on the plane at the tie and the other end free to radiate it. SNAA113’s remedy is blunt: ground the far end with a via as well, or leave the copper out entirely. Stitched pours are planes in miniature; ornamental pours are antennas.

Multiple converters, multiple boards

The star concept scales badly. With several converters, each one wants to be the point where analog and digital grounds join — several stars is no star. SLYT512’s multi-converter recipe keeps the partition and moves the star: on its worked eight-layer example with three DACs and two ADCs, the ground regions connect solidly under every converter, power enters the board in the digital partition and is filtered or regulated before it feeds the analog partition, and only the digital ground carries back to the supply.

Across a backplane, the plane itself has to be continuous from board to board: SLYT512 asks for 30 to 40% of the connector pins to be ground, tied to a continuous plane on the motherboard. From there the system ground is either multipoint — the backplane grounded to the chassis at numerous points, diffusing the return paths — or a single star at the supply, which is the usual choice for high-speed mixed-signal systems with separate analog and digital ground systems. One mechanical footnote from the same page: anodized aluminium is an insulator, and a chassis ground screwed into it is a drawing, not a connection.

A multicard system grounded through a backplane: each board connects to a continuous backplane ground plane through many connector ground pins, and the backplane ties to the chassis at numerous points, diffusing the return currents instead of concentrating them into one loop. — Fig 12 — Beyond one board the star breaks down, so the backplane becomes the plane: 30–40% of each connector’s pins carry ground, and the backplane grounds to the chassis at many points (or, in high-speed mixed-signal systems, at one star point at the supply).

The decision rule, restated

Default: one continuous ground plane. Partition the components, not the copper: analog region, digital region, converters on the boundary.
Route with discipline. No digital net in the analog region, on any layer. The return current under each trace does the isolating.
AGND and DGND both tie to the plane at the device, shortest possible. On a board with split planes, both tie to the analog plane — the converter is analog.
The star point sits directly under the converter — minimal length, no vias — with the V_Dig decoupling loop closed locally.
Split only for a reason you can name — high-resolution, low-speed precision, after the partitioned single plane has actually been found wanting — and then bridge the planes at one point and route every crossing over the bridge. Protect the pins across the gap (Schottky pair or ferrite bead), and leave a strap option to close the split if measurement says so.
No unstitched pours. Copper that does not carry return current in a tight loop is an antenna.

Sources

TI SLYT499 — Grounding in mixed-signal systems demystified, Part 1 — AGND/DGND pin meaning, the return-current distribution and its formula, the two EMC principles, low- versus high-digital-current schemes, Schottky and ferrite plane ties.
TI SLYT512 — Grounding in mixed-signal systems demystified, Part 2 — split-plane loop and dipole failures, the bridge, partitioning as the preferred method, the star point at the converter, multi-converter and multicard grounding.
TI SNAA113 — The problem of ADC and mixed-signal grounding and layout for dynamic performance while minimizing RFI/EMI — skin and proximity effects, the few-megahertz least-inductance threshold, radiation versus loop area, and the single-point-grounded pour antenna.

Updates

2026-09-13 — Corrected the return-current arrowheads in Figs 5, 7 and 10: the return flows from load to driver, antiparallel to the signal on every segment; three arrowheads had been drawn in the signal direction.
2026-09-13 — Fig 7 caption now points at Fig 2 for the return-current shadow; Fig 3’s detour curve darkened so the legend entry is legible in dark mode; Fig 9 labels moved apart.