The via is the decoupling: 40 dB from layout alone

The previous two articles argued that a decoupling capacitor is really an inductor above about 16 MHz, and that the value printed on it is not the value you get. Both are properties of the component. This one is about the part of the problem that is entirely yours: the loop you solder it into.

Würth ran the experiment properly, and the result is stark enough that it should change how you review a layout.

The experiment

From ANP098: a four-layer board designed for 50 Ω, six measurement channels, insertion loss S21 swept from 300 kHz to 3 GHz on an E5071C network analyser. Two channels calibrate the setup; the rest carry filters.

The critical detail is what was held constant. Every channel has the same 0603 ferrite and the same two 100 nF X7R capacitors. Same part numbers, same values, same count. The only differences are:

1. the MLCC package (0402, 0603, 0805) and therefore its ESL,
2. how many ground vias each capacitor pad gets,
3. how the capacitors are arranged relative to the ferrite,
4. how long the traces from pad to via are.

Three of those four are layout. None of them is “which capacitor”.

The result

Depending on the measurement point, there is a difference of more than 40 dB to the next best channel.

That is the deliberately bad channel: 0805 parts, a single ground via shared between both capacitors, unnecessarily long trace stubs to the pads, and the capacitors arranged parallel to the ferrite so they couple to it inductively and capacitively.

Forty decibels is a factor of one hundred in voltage. The filter did not degrade; it substantially stopped working. Nothing on the BOM would show it. A schematic review would pass it. Every part is correct and correctly valued.

And the other half of the result matters just as much:

If the basic layout rules such as 90° arrangement of MLCCs to ferrite and short pad connection to vias as well as traces are observed, a broadband filter can be successfully designed. The differences in the insertion loss are then only maximum 10 dB depending on the design and via count.

So: >40 dB between a bad layout and a good one, and ≤10 dB among all the good ones, across package sizes and via counts. Once the layout is sane, the choice of 0402 versus 0805 is a ten-decibel refinement. Before that, it is noise next to a hundredfold error.

The ordering is the lesson. Fix the loop first. Optimise the part afterwards, if at all.

Why the trace is the whole story

The number to memorise:

1–2 mm in length corresponds to approximately 0.5 nH of additional ESL.

Compare that with the body inductance of the capacitors themselves — 610 pH for an 0612, 870 pH for an 0603, 1250 pH for a 1206, from the AVX measurements in the first article.

A 2 mm trace from pad to via adds roughly as much inductance as the entire body of an 0402 capacitor. Route the capacitor 4 mm from its via and you have added more inductance than the part contains, which is the same as saying you paid for a capacitor and installed two of its parasitics.

This is why “place the decoupling capacitor close to the pin” is such an unsatisfying rule. Close to the pin is not the objective. Small loop is the objective — pad to via to plane to via to pad — and the pin is only one corner of it. A capacitor 1 mm from the pin with its ground via 3 mm away on the far side is worse than one slightly further out with its via directly against the pad.

Vias: more of them, and spread apart

Two effects, and they pull in opposite directions.

More vias lower the inductance. Ground vias in parallel divide like any other parallel inductance, so two vias per ground pad beat one, and three beat two. The best-performing channel on Würth’s board is the 0402 with three vias per ground pad, exactly as predicted.

Vias too close together stop helping. Vias carrying the same current in the same direction have a mutual inductance that adds to the total. The closer together they are, the more they couple, and the less each additional via buys you. Würth simulated this in EMCoS and state it directly: the further apart vias of the same potential are, the smaller the mutual inductance and therefore the smaller the total.

The resolution is a placement, not a compromise:

If the vias are placed at a 90° angle around the GND pad of the MLCCs, they can be connected close to the pad and still result in a large distance between the 3 vias.

Fan the vias out around the pad rather than stringing them along one side. Each one keeps its short connection to the pad, and they stay far enough apart not to couple. It costs nothing but a few seconds of placement.

The via calculator gives resistance and thermal numbers for a plated hole; for decoupling the figure that matters is the inductance of the loop it closes, which is a geometry problem your field solver or your judgement has to answer.

A layout checklist that follows from the measurement

• Ground via touching the pad. Not on a stub, not shared. If you can only fix one thing, fix this.
• Never share one via between two capacitors. That was a defining feature of the 40 dB channel.
• Two or three vias per ground pad, fanned out around it at roughly 90°, not clustered.
• No trace between pad and via where a direct connection will do. Every millimetre is ~0.25 nH.
• Cross the ferrite, do not run beside it. Parallel runs couple; the bad channel’s capacitors were arranged along the ferrite.
• More of the same part beats a spread of values. n identical parts give L/n without the anti-resonance a mixed set creates.
• Package last. Choose 0402 over 0805 when it is free, but do not trade a short via connection for a smaller body.

The part you can measure yourself

None of this needs a €40 000 network analyser to confirm on your own board. TI’s SLOA069 makes the same case for high-speed op amps using scope captures of the supply pin, which is equipment you have. Probe the rail at the device pin, with a short ground spring rather than the lead, while the thing switches. Then move the capacitor’s ground via and probe again.

The difference is not subtle. That is the point of the 40 dB.

Sources

• Würth ANP098 — Effect of layout, vias and design on the blocking quality of filter capacitors — the six-channel board, the S21 measurements, the >40 dB and ≤10 dB figures, the 0.5 nH per 1–2 mm, and the 90° via placement.
• Kyocera AVX — Parasitic Inductance of Multilayer Ceramic Capacitors — package ESL to compare the trace inductance against.
• TI SLOA069 — How (Not) to Decouple High-Speed Operational Amplifiers — the same argument with measured scope results.
• TI SPRABV2 — BGA decoupling and PDN design — via-in-pad and capacitor placement under a BGA, where none of the above is optional.