Decoupling capacitor calculator

A capacitor is only a capacitor below its self-resonance. This draws the impedance of a real part with its package and mounting inductance, sets the target impedance from the load step you have to serve, and counts how many of the part you need to stay under the line.

Fig 1 — |Z| of one part (thin) and 10 in parallel (bold); self-resonance at 15.9 MHz.

Capacitance (nF)

Package

Mounting inductance (nH)

ESR (mΩ)

Rail voltage (V)

Allowed ripple (%)

Load current step (A)

Step rise time (ns)

Lower band edge (MHz)

Parts to plot (0 = as needed)

Target impedance: 165 mΩ up to 175 MHz
Self-resonance of one part: 15.9 MHz (ESR 20.0 mΩ there)
Total inductance per part: 1.00 nH (0.40 body + 0.6 mount)
Parts needed, 1 MHz to 175 MHz: 10 (worst 1.59 Ω at 1.00 MHz)
|Z| of 10 at f_max: 109 mΩ ✓
|Z| of 10 at 100 kHz / 1 MHz / 100 MHz: 1.59 Ω · 159 mΩ · 61.3 mΩ
Charge for the step: 2.00 nC → 2.00 mV droop from capacitance alone

f_max is 11× the self-resonance: above 15.9 MHz these parts are inductors, and the value printed on them stops mattering. Lower the mounting inductance (via-in-pad, both vias inside the pads, thin dielectric to the plane) before adding more parts; above a few hundred MHz only plane capacitance and the package help.

How this is calculated

Standard: Series RLC capacitor model; target-impedance PDN method (Smith, Xilinx XAPP623 / UG483, ADI MT-101)

$|Z(f)| = \sqrt{\text{ESR}^2 + \left(2\pi f L - \frac{1}{2\pi f C}\right)^2}$: A real capacitor is a series RLC: capacitive below resonance, inductive above it.
$L = \text{ESL}_{body} + L_{mount}$: Mounting inductance — pads, vias and the trace to the plane — is usually the larger of the two.
$f_{srf} = \frac{1}{2\pi \cdot \sqrt{L \cdot C}}$: Self-resonance, where the impedance falls to the ESR.
$Z_{target} = \frac{V_{dd} \cdot \text{ripple}}{\Delta I}$: Ripple is the allowed supply variation as a fraction of V_dd; ΔI is the load current step.
$f_{max} \approx \frac{0.35}{t_{rise}}$: The top of the band the target impedance has to be held across, from the 10–90 % edge of the load step.
$N = \left\lceil \frac{\max |Z(f)|}{Z_{target}} \right\rceil$: Identical parts in parallel, with the maximum taken over the band.

Assumptions

Identical parts in parallel divide impedance by N exactly only if each has the same mounting inductance and the plane between them is short — spread them around the package.
Body ESL values are typical; the vendor SPICE model or S-parameters are better. Mounting inductance is usually the bigger number and is entirely yours.
No anti-resonance is modelled: mixing values creates impedance peaks between their self-resonances that this single-value model cannot show.
Plane capacitance, package inductance and on-die capacitance take over above a few hundred MHz; the model says nothing useful there.
ESR is taken as constant; in real MLCCs it rises below ~100 kHz and falls with frequency above.

What sets a decoupling capacitor's impedance

A capacitor is a series RLC. Below its self-resonant frequency the capacitance sets the impedance; above it, the inductance does, and the value printed on the part stops mattering. ESR is the floor at resonance. That is the |Z(f)| and f_srf pair under How this is calculated above.

The inductance in them is the package's body ESL plus whatever the mounting adds. Body ESL presets: 0201 0.3 nH, 0402 0.4 nH, 0603 0.6 nH, 0805 0.8 nH, 1206 1.2 nH, reverse-geometry 0306 0.2 nH. The mounting field is where the real number lives.

The second half is the target-impedance method from XAPP623: the rail has to stay under Z_target up to about f_max, both given above. For a band, the tool takes the worst impedance of one part and divides — N identical capacitors in parallel have 1/N the impedance, so N = ceil(Z_worst / Z_target). Identical parts only; mixed values are the anti-resonance section.

Self-resonant frequency chart

The frequency above which a decoupling capacitor is an inductor, for the common values in the common packages, computed by the calculator above from the body inductance of each size. These are ceilings: the vias, pads and trace that mount the part add inductance the body does not have, and the worked example below shows what 1 nH in total does to a 100 nF 0402.

Value	0402 (0.4 nH)	0603 (0.6 nH)	0805 (0.8 nH)	1206 (1.2 nH)
1 nF	252 MHz	205 MHz	178 MHz	145 MHz
10 nF	79.6 MHz	65.0 MHz	56.3 MHz	45.9 MHz
100 nF	25.2 MHz	20.5 MHz	17.8 MHz	14.5 MHz
1 µF	7.96 MHz	6.50 MHz	5.63 MHz	4.59 MHz
10 µF	2.52 MHz	2.05 MHz	1.78 MHz	1.45 MHz

Read across a row and the package matters less than expected: a 1206 resonates only 1.7 times lower than a 0402 of the same value. Read down a column and the value matters a great deal: every decade of capacitance costs a factor of 3.2 in frequency. That is the arithmetic behind the advice to reach for a smaller package before a smaller value, and behind the reason 100 nF cannot decouple anything above a few tens of megahertz on its own.

Worked example: a 100 nF 0402 with 1 nH of inductance

The part this site is named for: 100 nF, 0402, ESR 20 mΩ, 0.4 nH body, 0.6 nH mounting, 1 nH total.

f_srf = 1 / (2π √(1e-9 × 1e-7)) = 1 / (2π × 1e-8) = 15.9 MHz

at 100 kHz:  1/(2πfC) = 1/(2π × 1e5 × 1e-7) = 15.92 Ω
             2πfL     = 2π × 1e5 × 1e-9      = 0.0006 Ω
             |Z| = √(0.02² + (0.0006 − 15.92)²) = 15.9 Ω

at 15.9 MHz: reactances cancel              |Z| = ESR = 20 mΩ

at 1 GHz:    2πfL     = 2π × 1e9 × 1e-9      = 6.283 Ω
             1/(2πfC) = 1/(2π × 1e9 × 1e-7)  = 0.0016 Ω
             |Z| = √(0.02² + 6.28²)          = 6.28 Ω

At 1 GHz the part is a 1 nH inductor; a 1 nF in the same footprint reads the same 6.28 Ω.

Target impedance for a 1 V core rail, 5 % ripple, 10 A step, 1 ns edge:

Z_target = 1 V × 0.05 / 10 A  = 5 mΩ
f_max    = 0.35 / 1e-9        = 350 MHz

How many of the 100 nF above to hold a gentler 100 mΩ from 1 to 100 MHz:

at 1 MHz:    1/(2πfC) = 1.5915 Ω, 2πfL = 0.0063 Ω
             |Z| = √(0.02² + 1.585²)         = 1.59 Ω     ← worst in band
at 100 MHz:  2πfL = 0.628 Ω, 1/(2πfC) = 0.016 Ω
             |Z| = √(0.02² + 0.612²)         = 0.61 Ω
N = ceil(1.59 / 0.1)                         = 16 parts

Sixteen 100 nF parts to cover 1 MHz, where one 4.7 µF (34 mΩ there) would do it alone: bulk at the bottom of the band, small parts at the top. The 5 mΩ target is a plane and package problem, not a count.

Where the single-capacitor model stops being valid

Why 100 nF. At 1 nH it resonates at 16 MHz, the middle of the edge spectrum of 1990s logic. A 1 µF in the same footprint has an SRF of 5 MHz and the same 100 MHz impedance. The value is a habit; the inductance is the spec.

Mounting inductance is usually larger than the body. A via or a narrow trace is roughly 1 nH per millimetre. An 0402 with vias at the pad ends and the plane pair 0.2 mm down adds 0.3 to 0.5 nH. A 2 mm trace from pad to via adds 2 nH; vias 1.5 mm down to a mid-board plane add 1.5 to 3 nH more. Two capacitors sharing a via pair share its inductance and do not parallel. The 0.6 nH in the example is a good layout; 2 to 4 nH is a careless one, which puts the 100 nF SRF at 11 or 8 MHz and doubles or quadruples the 100 MHz impedance.

Mixed values anti-resonate. Put a 100 nF and a 10 nF side by side, each with 1 nH. Between their SRFs (16 and 50 MHz) the 100 nF is inductive and the 10 nF capacitive: a parallel LC tank, and the combined impedance peaks with a height set by ESR. At 30 MHz the 100 nF is 0.19 Ω inductive, the 10 nF 0.34 Ω capacitive, and the pair is 0.4 Ω, worse than the 100 nF alone. Decade ratios with low-ESR ceramics are the worst case. XAPP623 and UG483 use many values spaced about 3:1 with enough of each to flatten the peaks; the other school uses many identical parts and accepts a lower SRF for no peaks at all. Both work; one each of three decades does not.

Above 100 MHz the caps are gone. One 100 nF at 1 nH is 0.63 Ω at 100 MHz; forty are 16 mΩ, but the spreading inductance of the plane between them and the BGA is about as much. From roughly 100 MHz up the die is fed by the plane pair (a few hundred pF per square inch at 0.1 mm spacing, almost no inductance) and the package's own capacitance. The 5 mΩ, 350 MHz target above is met with a thin power-ground dielectric and on-package capacitance, not more 0402s.

Below the regulator's bandwidth it holds the rail. A switcher's loop closes at tens of kHz, an LDO's at a few hundred kHz. Between that and where the 100 nF parts arrive, a 10 to 100 µF bulk part carries the load; its ESR matters, and so does the regulator's stability with it.

ESR and ESL are constants here. Real MLCC ESR falls with frequency, and class 2 dielectrics lose capacitance with DC bias, which moves the SRF up. Expect a factor of two; a two-port shunt measurement on a VNA finds the rest.

Common decoupling mistakes

Choosing a capacitor by value for a high-frequency job. Above the SRF the value is irrelevant; choose the package and the mounting.
Placing the via at the end of a trace instead of at the pad. The trace adds more inductance than the whole body of the part.
Sprinkling 100 nF, 10 nF and 1 nF next to each pin "for broadband coverage". With one of each, that is two anti-resonance peaks and no broadband anything.
Expecting board capacitors to fix a die-level ripple problem. If the edge is 1 ns, the on-board network is finished by a few hundred MHz; the rest is package and plane.
Forgetting the DC bias on a small class 2 part. A 0402 100 nF 10 V X5R at 5 V may be 50 nF, and the SRF moves accordingly.