100nF

Where the buck ripple comes from, and why more capacitance didn't help

The textbook formula ΔV = I/(8Cf) is the special case where ESR is zero. In the regime most real designs sit in, output ripple is I·ESR — independent of capacitance, duty cycle and switching frequency alike.

By power integrityswitching regulatorscapacitors

A recognisable afternoon: the rail has more ripple than the budget allows, so you add another 22 µF. Nothing changes. You add two more. Still nothing. Somewhere around the fourth capacitor you start to suspect the scope.

The scope is fine. You are in the regime where output ripple does not depend on capacitance at all.

Two different things get called ripple

Before the maths, a distinction that saves a lot of wasted effort. TI’s SNVA871 splits the output of any switching regulator into two components with almost nothing in common:

  • Low-frequency output ripple — at the switching frequency, a few tens of millivolts, triangular or sawtooth. This is the inductor’s current ripple working against the output capacitor’s impedance. It is deterministic and calculable, and it is what the rest of this article is about.
  • High-frequency output noise — sharp spikes at the switching edges, tens of megahertz of ringing from the high di/dt loop. Nothing about the output capacitor’s capacitance affects it.

They need different fixes. Adding bulk capacitance for HF noise is the most common wasted board area in switching supplies.

The three components of the ripple you can calculate

The inductor current is a triangle: rising during the on-time, falling during the off-time, with a peak-to-peak value I_p2p set by the inductance and the duty cycle. All of that ripple current flows into the output capacitor, because the load takes the average. The capacitor turns it into a voltage three ways at once.

i_Ltriangular; peaks at the end of the on-timev_Cthe integral of i_L — a quarter period behind itv_ESRESR · i_L — exactly in phase with the currentonoffv_C peaks a quarter period latev_ESR peaks with the currentwhat the scope shows = v_C + v_ESR + an ESL spike at each edge
Fig 1 — One switching period. The capacitor term is the integral of the current, so it peaks a quarter-period late; the ESR term is the current scaled. Which one dominates is decided by the RC product, not by the capacitance alone.

The capacitive term. Charge accumulates as the integral of the current, so the voltage is the integral of a triangle — a piecewise parabola, and crucially it is a quarter-period behind the current. Setting ESR to zero, SLVA630 gives the expression everyone learns:

V_C = I_p2p / (8 · C · F_sw)

The resistive term. ESR turns the ripple current straight into a voltage, exactly in phase with it:

V_R = I_p2p · R_ESR

The inductive term. ESL responds to di/dt, so it contributes a spike at each switching edge rather than a smooth ripple. This is the part that shows up as HF noise.

The measured waveform is the sum. The mistake in the textbook treatment is presenting V_C as the answer, when TI are explicit that it is what you get by setting R = 0.

Which term wins is a question about RC

SLVA630 works the peak-to-peak ripple in three regimes, chosen by comparing the capacitor’s own R·C time constant against half the on-time and half the off-time:

Small RC (RC much less than both T_on/2 and T_off/2) — the capacitive term dominates. The familiar I/(8CF) is a good estimate and adding capacitance helps proportionally. This is where a designer using low-ESR ceramics on a high-frequency converter usually sits.

Large RC — and here is the sentence worth the price of the application note:

Equation 19 implies that for a large ESR output, voltage ripple is independent of capacitance. Voltage ripple is also independent of other variables such as duty cycle and switching frequency.

The ripple is just I_p2p · R_ESR. Not mostly; independent of capacitance. Every additional microfarad you add is doing nothing for ripple. If the parts you are adding are the same type, you are also adding their ESR in parallel — which does help, but only as 1/n, and far less than you expected from the capacitance you just paid for.

Intermediate RC — one extreme of the waveform is set by I_p2p · R alone and the other has to be computed properly. Most real designs with electrolytic or polymer output caps live here.

So the diagnosis for the wasted afternoon is: check what fraction of your ripple is I_p2p × ESR before adding capacitance. It is a one-line calculation from two datasheet numbers, and it tells you immediately whether more capacitance is the lever.

The three things that actually reduce it

Lower the ripple current. Every term above is proportional to I_p2p. A larger inductor, or a higher switching frequency, reduces the current ripple and therefore reduces all three voltage terms at once. This is the lever that always works, and it is the one people reach for last because it means changing the magnetics.

Lower the ESR — if you are in the large-RC regime. This usually means changing capacitor technology, not quantity: ceramic or polymer instead of aluminium electrolytic. Note the interaction with the previous article on DC bias: swapping a 47 µF electrolytic for a 47 µF ceramic gets you the low ESR you wanted, and then the ceramic loses most of its capacitance to DC bias. If you were relying on that capacitance for loop stability rather than for ripple, you have solved one problem and created another. Some regulators also require a minimum ESR for stability, and a pure-ceramic output can make them oscillate.

Add a second-stage filter — for the HF noise the first two do not touch. SNVA871 compares a post-stage LC filter against an LDO for exactly this. The LC is cheap and lossless but adds a resonance you must damp and a pole that can destabilise the outer loop if it lands inside the bandwidth; the LDO is clean and simple and costs you the dropout voltage as heat. Both are legitimate; the choice is a power budget question.

The other half of that fix is layout, and it is free: SNVA871 notes that integrating the high-frequency input capacitor and a shielded inductor reduces the high di/dt loop area, giving less ringing and lower noise coupling to the output. That loop — input capacitor, high-side switch, low-side switch — is the one that carries the sharp edges, and its area is decided entirely by where you put the input capacitor. Same argument as the decoupling loop, same solution.

You are probably measuring it wrong

A 10 nF of scope-probe ground lead inductance will manufacture ringing that is not on your board. Measuring switching-supply output ripple with the standard 15 cm ground clip is the single most common way to see 200 mV of “noise” on a rail that has 20 mV on it.

  • Use a ground spring on the probe tip, or the tip-and-barrel technique, so the measurement loop is a few millimetres rather than a hand’s width.
  • Probe across the output capacitor’s terminals, not at a connector.
  • Bandwidth-limit to 20 MHz when you want the LF ripple, and take the limit off when you are hunting the HF noise — they are different measurements and one scope setting cannot show both honestly.

If moving the ground lead changes the answer, the answer was the ground lead.

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