Buck converter output ripple calculator

The peak-to-peak ripple current a buck's inductor carries, and the output voltage ripple it becomes across a real capacitor — the exact waveform, the capacitor and ESR terms separately, and which one is actually in charge.

Fig 1 — one period at D = 0.27: 217 mA of triangular inductor current becomes 2.62 mV of output ripple (mixed regime).

Input voltage (V)

Output voltage (V)

Load current (A)

Inductance (µH)

Switching frequency (kHz)

Output capacitance (µF)

Capacitor ESR (mΩ)

Inductor ripple current: 217 mA peak-to-peak · 22 % of the load
Output ripple, exact: 2.62 mV peak-to-peak
Capacitor term ΔI/(8CF): 2.47 mV
ESR term ΔI·R: 1.09 mV
Datasheet models: 3.56 mV linear · 2.70 mV RMS
Regime: mixed — capacitor and ESR terms are comparable; the exact waveform decides
Duty cycle: 0.275 · on-time 550 ns

How this is calculated

Standard: TI SLVA630 — Output Ripple Voltage for Buck Switching Regulator; TI SNVA559 — Switching Regulator Fundamentals

$D = \frac{V_{out}}{V_{in}}, \qquad \Delta I = \frac{V_{out}\,(1 - D)}{L \, f_{sw}}$: SNVA559: the filtered output equals the pulse amplitude times duty cycle, and v = L·di/dt. During the off-time the inductor sees V_out for (1−D)/f_sw, which sets the ripple current.
$V_C = \frac{\Delta I}{8 \, C \, f_{sw}}$: SLVA630’s capacitor-alone term — its full model with the ESR set to zero. The familiar textbook expression, and only the whole answer when the ESR term below is negligible.
$V_R = \Delta I \cdot R_{ESR}$: SLVA630 Equation 19’s regime: when RC exceeds half of both the on-time and the off-time, the ripple is this and nothing else — independent of capacitance.
$V_{lin} = V_C + V_R, \qquad V_{rms} = \sqrt{V_C^2 + V_R^2}$: SLVA630 Equations 24 and 25, the hand-calculation models some datasheets use. TI puts the linear model’s error near 60 % and the RMS model’s near 15 %; neither depends on duty cycle.
$t_{max} = \max\!\left(0, \tfrac{T_{off}}{2} - RC\right)$: Where the exact waveform peaks, per SLVA630. The tool evaluates the piecewise closed-form waveform — the ESR triangle plus the capacitor’s parabola — at these extrema rather than using either approximation.

Assumptions

Continuous conduction and an ideal switch: duty is V_out/V_in, and losses that push the real duty higher are ignored. The tool flags DCM when the load falls under half the ripple current.
ESL is excluded. The spikes at each switching edge ride on top of this ripple and answer to layout and the capacitor’s inductance, not to C and ESR.
C is the capacitance at the DC operating point. Class II ceramics lose a large fraction of their marked value to DC bias — derate before entering.
The ESR is taken at the switching frequency; electrolytic ESR rises steeply as temperature falls.
Ripple is what appears across the capacitor terminals. Measured at the end of a long ground clip it will be something else entirely.

What sets a buck converter's output ripple

A buck converter's inductor current is a triangle: it ramps up while the switch is on, down while it is off, and the load takes the average. The whole triangle — the ripple current ΔI — flows into the output capacitor, which turns it into voltage two ways at once: the capacitance integrates it into a parabola a quarter-period behind the current, and the ESR scales it into a triangle exactly in phase with it.

The textbook answer, ΔI/(8CF), is only the first of those. TI SLVA630 is explicit that it is the full model with the ESR set to zero, and works out what happens when it is not: below a certain RC product the capacitor rules and more capacitance helps, above it the ripple is ΔI·ESR — independent of capacitance, duty cycle and frequency all at once. The tool evaluates the exact piecewise waveform at the extremum SLVA630 locates (T_off/2 − RC), so it is correct across all three regimes, and shows the two hand-calculation models beside it with the errors TI measured for them.

The ripple current itself is derived, not looked up: SNVA559's two quoted facts — the output is the pulse amplitude times the duty cycle, and v = L·di/dt — fix the off-time volt-seconds, and ΔI follows. The same number sets the 20–30 %-of-load band the inductor is conventionally sized into, the CCM boundary, and the current the output capacitor has to swallow as heat.

Worked example: 12 V to 3.3 V at 1 A, 22 µH and 22 µF

The defaults: 12 V in, 3.3 V out, 1 A load, 22 µH, 500 kHz, 22 µF with 5 mΩ of ESR — a ceramic-output point-of-load buck.

D       = 3.3 / 12                       = 0.275
ΔI      = 3.3 × (1 − 0.275) / (22 µH × 500 kHz)
        = 3.3 × 0.725 / 11               = 217.5 mA   (21.8 % of 1 A)

V_C     = 0.2175 / (8 × 22 µF × 500 kHz) = 2.47 mV
V_R     = 0.2175 × 5 mΩ                  = 1.09 mV

RC      = 5 mΩ × 22 µF = 0.11 µs   T_on/2 = 0.275 µs   T_off/2 = 0.725 µs
        →  mixed regime; the exact waveform gives

V_p2p   = 2.62 mV     (linear model 3.56 mV, RMS model 2.70 mV)

The linear model overstates the ripple by a third here, which is its normal behaviour: the capacitor term peaks a quarter-period after the ESR term, so adding their individual peaks always overestimates the peak of the sum. With a 500 mΩ electrolytic in the same slot, RC reaches 11 µs, both extrema clamp to the switching instants, and the answer is simply 217.5 mA × 0.5 Ω = 109 mV — no amount of extra electrolytic capacitance changes it.

Where the ripple models stop being valid

Everything on this page assumes continuous conduction. When the load drops below ΔI/2 the inductor current touches zero, the converter (or its diode) stops the ramp, and duty cycle, ripple shape and formulas all change — the tool flags it rather than modelling it. Modern synchronous parts in forced-PWM mode stay in CCM at light load; parts in power-save mode do something proprietary that no closed form covers.

The high-frequency spikes on a scope shot are not in this model. They are the ESL of the capacitor and the loop inductance of the layout responding to the switch-node edges, and they answer to placement and via count, not to capacitance. Thebuck ripple articleseparates the three terms and explains why the spikes are a layout problem, not a capacitor-selection one.

C is the capacitance that survives the operating point. A 22 µF class II ceramic at 3.3 V may be most of its marked value; the same part on a 12 V rail may be less than half. Derate forDC bias first and give the tool the real number, or its regime call lands on the wrong side.

Common output ripple mistakes

Adding capacitance in the resistive regime. SLVA630's own sentence: for a large ESR output, ripple is independent of capacitance. Swap technology (polymer, ceramic) instead of quantity.
Sizing the inductor for minimum ripple instead of the 20–30 % band. A huge inductor slows the control loop and costs money and board area; ripple current is a design variable, not an enemy.
Entering the marked capacitance of a ceramic on a high rail. The DC bias derating comes first; the regime boundary moves with the real C.
Reading ripple with a long ground clip. The clip loop picks up the switch node and reports fiction; use a tip-and-barrel measurement at the capacitor before believing any number this tool is compared with.
Forgetting the input side. The output current is smooth but the input current is a square wave; the input capacitor sees far harsher RMS current than the output one, and this page says nothing about it.