Smoothing capacitor calculator for a rectifier: ripple, valley voltage and capacitance

The capacitance a bridge, centre-tap or half-wave rectifier needs to hold its output above a valley voltage, or within a peak-to-peak ripple, for a constant-power load such as a switching converter or a constant-current load such as a linear regulator; or, run the other way, the valley and ripple a given capacitor leaves. It solves TI's bulk-capacitance equation exactly, with the diode drops added, and shows the discharge window, the short conduction time and the pulse current the diodes carry, beside the textbook ripple approximation.

Fig 1 — Bridge from 85.0 V RMS at 50.0 Hz into 107.6 µF and 70.6 W constant power: the capacitor charges along the rectified sine to V_pk = 120 V, carries the load alone for t_d = 7.05 ms down to V_min = 72.1 V, and the diodes put the charge back in the t_c = 2.95 ms left of each 10.0 ms ripple period.

Solve for

Rectifier

Minimum input voltage V_in (RMS) (V)

Line frequency f (Hz)

Diode forward voltage V_F, per diode (V)

Load type

Power drawn from the capacitor P (W)

Valley voltage V_min (V)

Maximum input voltage V_max (RMS), for ratings (V)

Hold-up end voltage V_hold (optional) (V)

Minimum capacitance C, before tolerance and ageing: 107.6 µF
Peak V_pk = √2·V_in − 2·V_F · valley V_min · ripple ΔV: 120 V · 72.1 V · 48.1 V
Valley as a share of the peak: 60.0 %
Ripple frequency · period T_r: 100 Hz · 10.0 ms
Capacitor alone, peak to valley, t_d · diodes conducting, t_c: 7.05 ms · 2.95 ms (29.5 % of T_r)
Textbook ΔV ≈ I/(f_r·C), with I = P/V_mid, would ask for: 152.7 µF, 42 % more
Charge given up and put back each period, Q = C·ΔV: 5.17 mC
Diode current averaged over the pulse: a floor on the peak: 2.45 A, 3.4 × the load's 723 mA
Average forward current in each diode, which conducts every other pulse: 361 mA
With the diodes conducting past the peak, 107.6 µF holds a valley of: 73.7 V, 1.60 V higher
Hold-up if the line fails at a peak, down to V_min: 7.05 ms: the discharge window itself
Capacitor voltage rating, at least √2·V_max at no load: 424 V
Diode reverse voltage, √2·V_max: 424 V

Whether 72.1 V is enough depends on what follows the capacitor: a linear regulator needs its output plus its dropout, a converter its minimum input. The valley is the input that circuit sees at its worst.

How this is calculated

Standard: TI UCC28740 datasheet (SLUSBF3D), §8.2.2.3, Equation 11; TI TIDUB51 60 W reference design, §4.2.2; Vishay DF005S–DF10S bridge rectifier datasheet (88573)

$C_{BULK} = \frac{2P_{IN} \times \left(0.25 + \dfrac{1}{2\pi} \times \arcsin\!\left(\dfrac{V_{BULK(min)}}{\sqrt{2} \times V_{IN(min)}}\right)\right)}{\left(2V_{IN(min)}^{2} - V_{BULK(min)}^{2}\right) \times f_{LINE}}$: UCC28740 Equation 11, as printed: "Equation 11 provides an accurate solution for the total input capacitance based on a target minimum bulk-capacitor voltage. Alternatively, to target a given input capacitance value, iterate the minimum capacitor voltage to achieve the target capacitance value." TIDUB51 works it for 70.6 W from 85 VAC at 50 Hz with a 72.14 V valley: C_BULK ≥ 107.7 µF.
$t_d = \frac{1}{f}\left(\frac{1}{4} + \frac{\arcsin x}{2\pi}\right) \;\text{(full-wave)}, \qquad t_d = \frac{1}{f}\left(\frac{3}{4} + \frac{\arcsin x}{2\pi}\right) \;\text{(half-wave)}, \qquad x = \frac{V_{min} + n V_F}{\sqrt{2}\,V_{in}}$: The discharge window, from the peak to where the next rising half-cycle reaches the valley. The full-wave form is Equation 11's own bracket. The half-wave form, a half period longer, and the diode drops inside the arcsine are derived here and are not in TI's documents; n is 2 for a bridge and 1 for a centre-tap or half-wave rectifier. With V_F = 0, x is Equation 11's arcsine argument.
$V_{pk} = \sqrt{2}\,V_{in} - n V_F, \qquad \tfrac{1}{2} C \left(V_{pk}^2 - V_{min}^2\right) = P\,t_d, \qquad C\left(V_{pk} - V_{min}\right) = I\,t_d$: The energy balance for a constant-power load and the charge balance for a constant-current one. With V_F = 0, V_pk² = 2V_IN² and the first, with the full-wave t_d, is Equation 11 exactly. For a given C the calculator finds V_min by bisection, which is TI's "iterate the minimum capacitor voltage".
$\Delta V \approx \frac{I}{f_r\,C}, \qquad f_r = 2f \;\text{(full-wave)}, \; f \;\text{(half-wave)}, \qquad \frac{C_{textbook}}{C} = \frac{T_r}{t_d}$: The textbook ripple, which has the capacitor carry the load for the whole ripple period T_r = 1/f_r. For a constant-power load it is fed I = P/V_mid, V_mid = (V_pk + V_min)/2, since ½C(V_pk² − V_min²) = C·ΔV·V_mid makes the exact discharge a constant current P/V_mid over t_d. The only difference left is the window, so the textbook figure is the zero-conduction-time limit and always the larger.
$t_c = T_r - t_d, \qquad \bar{I}_{pulse} = \frac{C\,\Delta V + Q_{load,c}}{t_c}$: The time the diodes conduct, and the mean current through them over that pulse: the charge the capacitor gets back plus what the load draws meanwhile (I·t_c, or ∫P/V dt along the sine). It is a floor on the peak diode current, not an estimate of it. Derived, not in TI.
$t_{hold} = \frac{C\left(V_0^2 - V_{hold}^2\right)}{2P} \;\;\text{or}\;\; \frac{C\left(V_0 - V_{hold}\right)}{I}$: Hold-up after the line fails, from V_0 = V_pk if it fails at a peak or V_0 = V_min if it fails at a valley, the worst case. From the peak to V_min it is t_d itself.
$V_{C,rated} \ge \sqrt{2}\,V_{max}, \qquad V_{R} = \sqrt{2}\,V_{max} \;\text{(bridge)}, \qquad V_{R} = 2\sqrt{2}\,V_{max} \;\text{(half-wave, centre-tap)}$: At the highest line and no load, with the diode drop left out so as to err high. The off diode in a bridge is tied through a conducting diode to the other rail and sees the capacitor voltage; in a half-wave or centre-tap circuit its anode swings to the negative source peak and it sees the sum. TIDUB51: "two capacitors (C2 and C3) with a 450-V rating need to be used to meet the maximum AC voltage rating of 300-V AC", and √2 × 300 V = 424 V.

Assumptions

Ideal rectifier: the source has no resistance, so the capacitor charges along the sine itself. Real transformer and wiring resistance lower the peak under load and widen the charging pulse; use the loaded secondary voltage for a transformer supply.
The diodes stop conducting at the peak, as in TI's equation. They in fact conduct a little past it, which raises the valley: the calculator shows that valley too (derived, not in TI), and the peak-departure result is the conservative one.
A constant forward voltage per diode. It rises with current, and the rectifier carries the charging pulse; enter V_F at the pulse current.
A steady load, either constant power (a switching converter's input, P = output / efficiency) or constant current (a linear regulator). A resistive load draws less current as the voltage falls, so entering its current at the peak, V_pk/R, as a constant current errs on the safe side.
The capacitance entered or returned is what the capacitor has at its worst: low tolerance, end of life, coldest. The ESR step and ripple-current heating are not modelled.

What sets a smoothing capacitor's value

A rectifier on its own delivers a string of half-sines. The reservoir capacitor after it turns that into something a regulator can use, and the way it does so sets its size. Through each half-cycle the capacitor charges along the rising sine to the peak. Just past the peak the sine starts to fall faster than the load can discharge the capacitor, the diodes stop conducting, and the capacitor carries the load on its own. Its voltage falls until the next half-cycle rises to meet it, at the lowest point of the ripple: the valley, V_min. The diodes then conduct again, and in the short time left before the next peak they put back all the charge the load took.

So the capacitor's value is set by three things: how much the load takes, how long it has to supply it alone, and how far its voltage may fall. The time alone is the discharge window t_d, from the peak to the point on the next half-sine where the source has climbed back to V_min. Measured in line phase from a zero crossing, the peak is at 90° and the next half-cycle of a full-wave rectifier reaches V_min at 180° + arcsin(V_min/√2·V_in), with no diode drop, so the window is a quarter of a line period plus that arcsine. A half-wave rectifier skips the negative half-cycle and the window is a whole half period longer. The lower the valley is allowed to go, the earlier the next half-cycle catches it and the shorter the window, which is why the capacitance falls faster than linearly as more ripple is accepted.

TI's UCC28740 flyback controller datasheet writes the result for a constant-power load, the input of a switching converter, as its Equation 11, and the reference note below typesets it. It is an energy balance: the energy the capacitor gives up between its peak and the valley, ½C(V_pk² − V_min²), equals the power times the discharge window. The datasheet is plain about it: "Equation 11 provides an accurate solution for the total input capacitance based on a target minimum bulk-capacitor voltage. Alternatively, to target a given input capacitance value, iterate the minimum capacitor voltage to achieve the target capacitance value." The calculator does both: it solves Equation 11 for C, and it runs the iteration by bisection when C is given.

A linear regulator draws a constant current instead, and the discharge is a straight line: C·ΔV = I·t_d. The discharge window is the same geometry. The capacitor's peak is the source peak less the diodes in the conducting path: two in a bridge, one in a centre-tapped transformer or a half-wave rectifier. Equation 11 has no diode drop, as is reasonable for an offline supply where two drops of a volt or so are lost against a 120 V peak. On a 12 V transformer it is not, and the calculator subtracts it both from the peak and inside the arcsine, where it moves the point at which the next half-cycle catches the capacitor.

The ripple voltage formula for a full-wave rectifier in most textbooks is ΔV ≈ I/(2fC), and for a half-wave rectifier ΔV ≈ I/(fC). Both assume the capacitor supplies the load for the whole ripple period: 10.0 ms after a bridge on 50 Hz mains, 20.0 ms after a half-wave rectifier. The real window is shorter by the conduction time, so the textbook ripple is an upper bound and the capacitance it asks for is too large by the ratio of the ripple period to t_d. In TI's example below that is 42 % more capacitance; at the small ripple of a linear supply it is closer, 18 % in the 12 V example. The calculator shows the textbook figure beside the exact one so the difference is visible. For a constant-power load it feeds the textbook formula the current P/V_mid, where V_mid is halfway between peak and valley, because the exact energy balance reduces to exactly that constant current over t_d; the only difference left is the window.

Bulk capacitor chart: microfarads per watt at 85, 115 and 230 VAC

The bulk capacitance a bridge rectifier needs ahead of a switching converter, per watt drawn from the capacitor, from Equation 11. Multiply by the converter's input power, its output power divided by its efficiency, and then add the capacitor's tolerance and ageing on top. The valley is given as a share of the peak of that line voltage, the way TI's reference design specifies it; the diode drops are left out, as Equation 11 leaves them out.

Minimum line	Valley 60 % of peak	Valley 70 % of peak	Valley 80 % of peak
85 VAC, 50 Hz	1.52 µF	2.03 µF	3.06 µF
85 VAC, 60 Hz	1.27 µF	1.69 µF	2.55 µF
115 VAC, 50 Hz	0.833 µF	1.11 µF	1.67 µF
115 VAC, 60 Hz	0.694 µF	0.923 µF	1.39 µF
230 VAC, 50 Hz	0.208 µF	0.277 µF	0.418 µF
230 VAC, 60 Hz	0.173 µF	0.231 µF	0.348 µF

Two patterns are worth reading off it. The capacitance goes as the inverse square of the line voltage: a supply that only has to run from 230 VAC needs 1/7.3 of the capacitance per watt of one that must start at 85 VAC, which is why universal-input supplies carry such large bulk capacitors. And the frequency matters less than the valley: 60 Hz saves 17 %, while letting the valley fall from 80 % to 60 % of the peak cuts the capacitance to 50 % of what it was, at the price of a converter that must work from a lower input.

Filter capacitor for a full-wave rectifier and a linear regulator

For a low-voltage linear supply the load is a constant current and the ripple is usually specified directly. The table is for a 12 VAC secondary at 50 Hz through a Vishay DF-S bridge, taking the datasheet's maximum forward voltage of 1.1 V per diode at 1.0 A, which leaves a capacitor peak of 14.8 V. Each entry is the minimum capacitance for that load current and peak-to-peak ripple.

Load current	ΔV = 1.00 V	ΔV = 2.00 V	ΔV = 3.00 V
250 mA	2225 µF	1055 µF	673.2 µF
500 mA	4451 µF	2110 µF	1346 µF
1.00 A	8902 µF	4220 µF	2693 µF

The capacitance scales exactly with the current, since the discharge is linear. It scales a little less than inversely with the ripple, because a deeper valley is met earlier by the next half-cycle. A constant current also has a property that is easy to miss: for a given ripple, the diode drops do not change the capacitance at all. They move the peak and the valley down together, and the next half-cycle catches the capacitor at the same phase. What they change is where the valley sits, which is what the regulator after the capacitor cares about.

Worked example: TI's 60 W flyback from 85 VAC

TI's TIDUB51 reference design, a 60 W, 24 V flyback built around the UCC28740, works the same equation in its section 4.2.2. Its input power is 60 W at 85 % efficiency, and "Input capacitance value, C_BULK, is based on the maximum load power, converter efficiency, minimum operational input voltage, and minimal operational input frequency." For the valley: "The minimum recommended valley voltage on the input bulk capacitors is taken as 60% of the peak of the minimum AC voltage." The left column is the calculator's arithmetic; the right is what TI prints.

power      P_IN = 60 W / 0.85                             = 70.59 W    TI: 70.6 W
valley     V_BULK(min) = 85 × √2 × 0.6                    = 72.12 V    TI: 72.14 V
arcsine    x = 72.14 / (√2 × 85)                          = 0.6001    
window     t_d = (0.25 + arcsin(x)/2π) / 50 Hz            = 7.05 ms   
energy     C = 2 × 70.6 × t_d / (2 × 85² − 72.14²)        = 107.6 µF   TI: ≥ 107.7 µF
fitted     82 µF × 2 = 164 µF, valley at 50 Hz            = 88.7 V    
           164 µF, valley at 47 Hz                        = 86.7 V     TI: 86.7 V
rating     √2 × 300 VAC                                   = 424 V      TI: 450 V parts

The capacitance agrees with TI's to 0.05 %: the calculator gives 107.6 µF where TI prints 107.7 µF, a difference no single rounding of π, √2 or the arcsine accounts for, and small enough to be TI's intermediate rounding. TI's 72.14 V valley is itself slightly above 85 × √2 × 0.6, which is 72.12 V; the calculator is fed TI's printed figure.

TI then fits more than the minimum: "To meet the needs of hold up time, bulk capacitance is selected higher than this calculated value. The bulk capacitor selected is 82 µF × 2 = 164 µF." And: "Using Equation 3 and C_BULK = 164 µF, V_BULK(min) = 86.7 V." Run at 50 Hz, the frequency of the 107.7 µF step, the inverse gives 88.7 V, not 86.7 V. At 47 Hz it gives 86.7 V, which is TI's figure. 47 Hz is the minimum line frequency in the design's Table 2, and the next equation in the same section uses 47 Hz for "the longest period of the rectified line voltage". So the 86.7 V is the valley at the lowest frequency the design specifies, and 107.7 µF is not the minimum there: at 47 Hz the 72.14 V valley would need 114.5 µF. Both are correct for their frequency; the lesson is to size at the lowest line frequency the product will see, as TI's own text says.

At 47 Hz and 164 µF the capacitor carries the load for 8.05 ms of each 10.6 ms ripple period, and the diodes conduct for the remaining 2.59 ms. TIDUB51 goes on to estimate a charge time and an RMS ripple current from its own Equations 5 and 7; this page computes the conduction time from the waveform geometry instead, as the ripple period less the discharge window, and gives the average diode current over that pulse rather than an RMS figure.

For the voltage rating the design uses the top of its range, not the nominal: "For this design, two capacitors (C2 and C3) with a 450-V rating need to be used to meet the maximum AC voltage rating of 300-V AC." √2 × 300 V is 424 V, under the 450 V rating. The calculator's defaults are this example: 85 VAC, 50 Hz, a bridge with no diode drop, 70.6 W and a 72.14 V valley.

Worked example: a 12 V linear supply with a DF-S bridge

A 12 VAC transformer secondary at 50 Hz, a Vishay DF-S bridge, and a linear regulator drawing a steady 1 A, with 2 V of ripple allowed. Vishay's datasheet gives the "Maximum instantaneous forward voltage drop per diode" as 1.1 V at 1.0 A, and two diodes conduct at a time.

peak       V_pk = √2 × 12 − 2 × 1.1                       = 14.77 V   
valley     V_min = 14.77 − 2                              = 12.77 V   
arcsine    x = (12.77 + 2.2) / (√2 × 12)                  = 0.8821    
window     t_d = (0.25 + arcsin(x)/2π) / 50 Hz            = 8.44 ms   
charge     C = 1 A × t_d / 2 V                            = 4220 µF   
textbook   C = I / (2f·ΔV) = 1 / (2 × 50 × 2)             = 5000 µF   
pulse      t_c = 10 ms − t_d                              = 1.56 ms   
           mean diode current in the pulse, 1 A × 10 ms / t_c = 6.41 A

The textbook I/(2fC) asks for 5000 µF, 18 % more than the 4220 µF the geometry needs, because it assumes the capacitor supplies the load for the full 10.0 ms. Either will do the job; the point is that the textbook figure is a safe overestimate, not the answer. Leaving the diode drops out entirely gives the same 4220 µF, for the reason above, but it puts the valley at 15.0 V on paper where the real one is at 12.8 V. For a regulator that needs its output voltage plus its dropout, those 2.20 V can be the difference between regulating and not.

The same supply with a centre-tapped transformer, 12 V a side and one diode in the path, needs the same 4220 µF and sits 1.10 V higher. With a single diode, half-wave, it needs 9220 µF: 2.18 times as much, because the capacitor waits a whole 20.0 ms between pulses.

Two lines on the datasheet deserve a look against this example. The bridge's "Maximum average forward output rectified current" is 1.0 A at an ambient of 40 °C, with the part mounted on 13 mm × 13 mm copper pads, and the example draws exactly that. And the charge goes back in a 1.56 ms pulse whose current averages 6.41 A, 6.4 times the load, and peaks higher still: the 1.1 V drop is specified at 1.0 A, and in the pulse the diodes are well past it. The reverse voltage is modest, √2 × 12 V = 17.0 V on each diode of the bridge at the nominal secondary, against 50 V for the lowest grade, the DF005S; half-wave it would be 33.9 V. Use the transformer's unloaded secondary at the highest mains for V_max, not its nominal rating.

Where the ideal-rectifier model stops being valid

The diodes stop at the peak. Equation 11, and the calculator's main result, have the capacitor leave the sine exactly at its peak. In fact the diodes conduct a little longer, until the sine falls as fast as the load discharges the capacitor. The capacitor then starts its discharge slightly later and lower, with less time to go before the next half-cycle, and the valley comes out higher. The calculator solves that case too, a derivation that is not in TI's documents, and checks it against a time-step simulation of the ideal circuit in its tests. On TI's example it lifts the valley of the 107.6 µF capacitor from 72.14 V to 73.7 V, and of the 164 µF one at 47 Hz from 86.7 V to 87.4 V; on the 12 V example the change is only 15.3 mV. Equation 11 therefore errs on the safe side, by more when the ripple is large.

The source has no resistance. The model charges the capacitor along the sine itself, as if the line or the transformer could deliver any current. A real transformer's winding resistance and leakage inductance, the mains wiring and any inrush resistor all sit in the charging path. They lower the peak the capacitor reaches under load, so the real valley is lower than the calculator's, and they widen the charging pulse and lower its peak current. For a transformer supply the loaded secondary voltage, from the transformer's datasheet at the load current, is a better V_in than its nominal rating.

V_F is not a constant. A diode's forward voltage rises with its current, and the rectifier carries the charging pulse, not the load current. The DF-S datasheet's 1.1 V is a maximum at 1.0 A, and its Fig. 3 plots the typical forward characteristic per diode. Enter the drop at the pulse current the calculator reports, and on a low-voltage supply check the valley with the worst-case figure.

The capacitance is a minimum. The C the calculator gives is what the capacitor must still have at the end of its life, at the low end of its tolerance, at its coldest. The capacitor's datasheet gives its tolerance and the capacitance loss it allows over its rated life. Divide the result by the tolerance and the loss the datasheet allows, so that a part that is low on both still meets it. TI's own choice of 164 µF against a computed 107.7 µF is margin for hold-up time on top of that.

ESR and ripple current. The capacitor's equivalent series resistance adds a step to the ripple at each charging pulse, and the pulse current heats it. The calculator reports the average diode current over the pulse as a floor on the peak; the RMS ripple current, which the capacitor's rating is written against, depends on the pulse shape, and so on the source resistance the model leaves out. Measure it or simulate it with the real transformer, and choose a capacitor whose ripple-current rating at the ripple frequency covers it.

Switch-on. An empty capacitor is a short circuit to the rectifier for the first half-cycle. The DF-S bridge is rated for a peak forward surge current of 50 A, a "single half sine-wave superimposed on rated load". A large offline bulk capacitor usually needs an inrush limiter to stay inside a rating like that.

Common smoothing capacitor mistakes

Using the full-wave ripple formula for a half-wave rectifier. A half-wave rectifier recharges once per line cycle. On the 12 V example the full-wave textbook figure, 5000 µF, is well short of the 9220 µF half-wave rectification needs.
Getting the ripple frequency wrong. After a bridge or a centre-tapped transformer the ripple is at twice the line frequency, 100 Hz or 120 Hz; after a half-wave rectifier it is at the line frequency. The ripple rejection of the regulator after the capacitor, and the capacitor's ripple-current rating, have to be read at that frequency.
Forgetting the diode drops at low voltage. Two drops of 1.1 V are 2 % of an 85 VAC peak and 13 % of a 12 V transformer's. They move the whole ripple waveform down, valley included.
Rating the capacitor for the nominal line. On a universal-input supply √2 × 230 V is 325 V; the top of TIDUB51's 265 VAC input range gives 375 V, and the 300 VAC maximum TI rates the capacitors for gives 424 V. The rating comes from the highest voltage the capacitor will ever see, at no load, when nothing pulls the peak down.
Treating ΔV ≈ I/(2fC) as exact. It is the zero-conduction-time limit and overstates the ripple for a given capacitor, by more as the ripple grows. It is safe, but it hides what it leaves out: the diodes have only the conduction time to put the charge back.
Sizing at the typical line frequency. At 47 Hz TI's 72.14 V valley needs 114.5 µF instead of 107.6 µF; size at the lowest frequency the product will meet.
Ignoring the ripple-current rating. The capacitor passes the full charging pulse, averaging 2.45 A in TI's example against an average load current of 723 mA. A capacitor with enough microfarads and too little ripple-current rating runs hot and ages early.