MOSFET level shifter calculator

A level shifter connects two sections of a bus that run from different supplies. For an open-drain bus like I²C the shifter is one N-channel MOSFET per line: gate to the lower supply, source to the low-voltage bus, drain to the high-voltage bus, pull-ups on both sides. With nothing pulling, the FET is off and each side rests at its own rail; when either side pulls low, the FET conducts and the other side follows. For a 3.3 V to 5 V bus with 4.7 kΩ pull-ups and 100 pF each side, the FET has 2.9 V of gate drive, the pulling device sinks 1.6 mA, and each side rises in 398 ns — over Fast-mode's 300 ns, so 3.3 kΩ. Enter the two supplies, the pull-ups, the capacitances and the FET's threshold and on-resistance to check every state of the circuit against the I²C limits.

Fig 1 — Release from the low side: the 3.30 V bus rises on its own pull-up, the FET turns off once the source is within 1.50 V of the gate (371 ns), and only then does the 5.00 V bus rise on its own pull-up. The bar is the mode's 30–70 % rise-time limit.

I²C mode

V_DD1, low side (gate) (V)

V_DD2, high side (V)

Pull-up, low side (Ω)

Pull-up, high side (Ω)

Bus capacitance, low side (pF)

Bus capacitance, high side (pF)

MOSFET V_GS(th), max (V)

R_DS(on) at the available drive (Ω)

Body diode V_F (V)

Driver V_OL (V)

Gate drive V_DD1 − V_OL · margin over V_GS(th): 2.90 V · 1.40 V
State 3: V_DD1 needed to pull the low side through the body diode: 2.60 V
Sink current for the pulling device · mode limit: 1.60 mA · 3.00 mA
Low level on the far side: high side · low side: 402 mV (V_IL 1.50 V) · 401 mV (V_IL 990 mV)
Rise time 30–70 %: low side · high side · limit: 398 ns · 398 ns · 300 ns — over
FET turn-off delay after a low-side release: 371 ns

398 ns of rise time is over the mode's 300 ns: a smaller pull-up on that side, less capacitance, or the slower mode. The high side also starts 371 ns late, which the mode's timing budget has to absorb.

How this is calculated

Standard: Nexperia AN10441; NXP UM10204 limits; TI SCEA030

$V_{GS} = V_{DD1} - V_{OL} > V_{GS(th)}$: AN10441 state 2: a low-side pull-down turns the FET on.
$V_{DD1} > V_{OL} + V_F + V_{GS(th)}$: AN10441 state 3: the body diode drags the low side down until the FET takes over.
$I_{sink} = \frac{V_{DD1} - V_{OL}}{R_{p1}} + \frac{V_{DD2} - V_{OL}}{R_{p2}} \leq I_{OL}$: The pulling device carries both pull-ups; 3 mA in Standard and Fast mode, 20 mA in Fast-mode Plus (UM10204).
$V_{low,far} = V_{OL} + \frac{V_{DD,far} - V_{OL}}{R_{p,far}} R_{DS(on)} \leq 0.3\, V_{DD,far}$: The far side's low level through the FET, against the I²C V_IL.
$t_r = 0.8473\, R_p C_b \text{ per side}$: 30–70 % rise time, UM10204 table 11; each side has its own R and C.
$t_{off} = R_{p1} C_1 \ln \frac{V_{DD1}}{V_{GS(th)}}$: After a low-side release, the high side is held until the source rises to V_DD1 − V_GS(th).

Assumptions

The FET is fully on or fully off; R_DS(on) is the value at the gate drive available, entered by the user, and the threshold is the datasheet maximum.
The body diode drop is fixed at V_F; the FET's own capacitance is included in the two bus capacitances by the user.
V_IL is the I²C 0.3·V_DD; devices with a fixed V_IL differ.
The rise times are the plain RC of each side; the high side's delay is reported separately and is not added to its rise time.
Standard and Fast mode only, per AN10441; the Fast-mode Plus limits are included for the sink current and rise time but the note does not cover it.

What sets whether a MOSFET level shifter works

A level shifter is needed when two devices with different supplies have to talk and the lower one is not tolerant of the higher rail — or, in the other direction, when a low swing "simply does not have enough logic swing to pass through the input V_IH level of the receiving device" (TI SCEA030). For a bidirectional open-drain bus the shifter must work both ways with no direction pin, and Nexperia's AN10441 gives the circuit that does: one N-channel MOSFET per line, "the gates connected to the lowest supply voltage V_DD1, the sources to the bus lines of the 'lower-voltage' section, and the drains to the bus lines of the 'higher-voltage' section", with pull-ups on both sides to their own rails.

The note walks its three states. Nobody pulling: gate and source both at V_DD1, "V_GS is below the threshold voltage and the MOSFET is not conducting", so each side sits at its own rail — that is the level shift. A low-side device pulls: the source drops, "V_GSrises above the threshold and the MOSFET starts to conduct", dragging the high side down through it. A high-side device pulls: "the drain-substrate diode of the MOSFET" pulls the low side down "until V_GS passes the threshold and the MOSFET starts to conduct", and the low side follows to the same low. States 2 and 3 are the wired-AND the I²C specification requires; state 1 is the shifting.

Every one of those states has a number in it, and the calculator checks each. The gate drive is only V_DD1 − V_OL, so the FET's threshold must be comfortably below that — the reason a 1.8 V low side needs a low-threshold part. State 3 has to get the low side to V_OL + V_F + V_GS(th) through the body diode before the FET takes over, which is a second, stricter, condition on V_DD1. Whichever device pulls low sinks both pull-ups through the conducting FET, against the mode's specified sink current. The far side's low level is V_OL plus its own pull-up current through R_DS(on). And each side rises on its own RC when released, with the high side unable to start until the low side has risen within V_GS(th) of the gate and switched the FET off.

Worked example: 3.3 V to 5 V I²C, 4.7 kΩ each side, 100 pF each

The calculator's defaults: a 3.3 V controller section and a 5 V peripheral section, AN10441's own supplies, 4.7 kΩ pull-ups to each rail, 100 pF on each side, a FET with a 1.5 V maximum threshold and 2 Ω on at the available drive, checked as a Fast-mode bus.

gate drive     3.3 − 0.4                        = 2.9 V     margin 1.4 V over V_th 1.5 V
state 3        needs V_DD1 > 0.4 + 0.7 + 1.5     = 2.6 V     → 3.3 V is enough
sink           2.9 / 4.7k + 4.6 / 4.7k           = 1.60 mA   (limit 3 mA)
low on 5 V side  0.4 + 0.979 mA × 2 Ω            = 0.402 V   (V_IL 1.5 V)
rise, each side  0.8473 × 4.7 kΩ × 100 pF        = 398 ns    Fast-mode limit 300 ns — over
FET turn-off   4.7 kΩ × 100 pF × ln(3.3/1.5)     = 371 ns after the low side releases

for Fast-mode: R ≤ 300 ns / (0.8473 × 100 pF) = 3.54 kΩ → 3.3 kΩ: 280 ns, sink 2.27 mA

The levels and the sink current are fine; the rise time is the problem, and it would be the same problem without the shifter — 4.7 kΩ into 100 pF is a Standard-mode number. The shifter adds something the plain bus does not have: the high side's edge starts 371 ns after the low side's, because the FET holds it down until the low side has climbed to V_DD1 − V_GS(th). At 100 kHz that is invisible; at 400 kHz it is a third of the low period, and a lower-threshold FET shortens it as much as a smaller pull-up does.

Where the level shifter model stops being valid

Hs-mode and push-pull signals. AN10441 says the circuit "is not intended for Hs-mode systems", and it is an open-drain device: a push-pull driver on either side fights the FET. TI's auto-direction translators — the switch-type TXS for open-drain, the buffered TXB for push-pull — are the part for those.
R_DS(on) at low gate drive. The datasheet headline is at 4.5 or 10 V of gate drive; at 2.9 V, or 1.4 V for a 1.8 V low side, it can be many times higher, and the far side's low level rises with it. Read the R_DS(on)-versus-V_GScurve at the drive actually available.
The body diode is not free. State 3's diode drop means the low side dips to about 1.1 V before the FET takes over; with a marginal threshold the FET never does, and the low side idles at a diode drop above ground — a valid low for most inputs, and not what the driver intended.
Capacitance of the FET. Its C_oss and C_iss add to both buses; small parts are tens of picofarads and appear in both capacitance entries, not in neither.
Power sequencing. AN10441 allows V_DD2 to fall below V_DD1 "during switching power on/off" only; with the high side unpowered its pull-ups are gone and the high bus is held at whatever the low side does, which the note counts as a feature — it "isolates a powered-down bus section from the rest of the bus system".

Common level shifter mistakes

Gate to the higher supply. With the gate at V_DD2 the FET conducts whenever the low side is below V_DD2 − V_th, which is always: the high side is pulled to the low rail and the shift is gone. Gate to the lowest supply.
Pull-ups on one side only. Each section needs its own, to its own rail; the FET does not carry a high across, only a low.
A logic-level FET chosen by its 10 V R_DS(on). The threshold is the number that matters, and for a 1.8 V side it has to be under a volt with margin.
Sizing the pull-ups as if there were one bus. The pulling device sinks both; two 2.2 kΩ pull-ups on a 3.3/5 V pair are 3.4 mA against a 3 mA specification.
Expecting the two sides to rise together. They do not; the high side waits for the FET to turn off. The I²C pull-up calculator sizes each side's resistor; this page adds the wait.