555 timer calculator

Astable frequency and duty cycle, or one-shot pulse width, worked from the LM555 datasheet's own equations — in both directions, so you can also ask which resistors land on the frequency you want.

Fig 1 — the capacitor sawtoothing between ⅓ and ⅔ VCC: 14.6 kHz at 69.7 % duty.

Mode

Solve for

RA (kΩ)

RB (kΩ)

Timing capacitor (nF)

Supply (V)

Frequency: 14.6 kHz · period 68.6 µs
Duty cycle: 69.7 % high
Output high / low: 47.8 µs · 20.8 µs
Discharge pin current: 1.11 mA as the low phase begins

How this is calculated

Standard: TI LM555 datasheet (SNAS548D) — Equations 1–5 and the monostable section

$t_{high} = \ln 2 \,(R_A + R_B)\,C, \qquad t_{low} = \ln 2 \, R_B \, C$: Datasheet Equations 1 and 2, which print the constant as 0.693. It is ln 2 exactly: the capacitor crosses from ⅓ to ⅔ of the supply, which is one half of the remaining gap in both directions.
$T = \ln 2 \,(R_A + 2R_B)\,C, \qquad f = \frac{1}{T}$: Equations 3 and 4. The charge path runs through both resistors and the discharge path through RB alone, which is the whole reason the duty cycle is asymmetric.
$D = \frac{R_A + R_B}{R_A + 2R_B}$: Equation 5. It exceeds 50 % for every positive RA and approaches it only as RA vanishes — so the tool refuses to design for 50 % or below rather than returning a negative resistor.
$t_{pulse} = \ln 3 \, R_A \, C$: The monostable, printed in the datasheet as 1.1 RA C. The capacitor starts at zero and stops at ⅔ VCC, which is ln 3 = 1.0986 time constants; the datasheet’s rounding runs 0.13 % long.
$R_A = \frac{(2D - 1)\,T}{\ln 2 \cdot C}, \qquad R_B = \frac{(1 - D)\,T}{\ln 2 \cdot C}$: The same equations rearranged for the component solve; the results are also shown snapped to E24.

Assumptions

Timing is independent of supply voltage — the datasheet states this explicitly, because both the charging voltage and the comparator thresholds scale with VCC. The supply entered here is only used for the range check and the discharge-pin current.
The LM555 timing error is specified over RA = 1 kΩ to 100 kΩ with C = 0.1 µF; outside that the equations still compute but the datasheet’s accuracy does not apply, and the tool says so.
Initial accuracy is about 1 % monostable and 2.25 % astable (typical) before the tolerance of your own R and C, which usually dominates everything.
Ideal switching: the discharge transistor’s saturation voltage and the comparator delays are ignored, which is why very small resistors and very high frequencies drift from these numbers.
The classic topology only. A diode across RB, a CMOS variant (LMC555, TLC555) or a 50 % duty configuration each change the equations.

What sets a 555's frequency and duty cycle

The 555 is two comparators, a flip-flop and a transistor, wired so that a capacitor is forced to shuttle between one third and two thirds of the supply. Everything the chip does follows from that: the timing intervals are just the RC crossings between those two thresholds, which is why the datasheet's famous constants are logarithms wearing a disguise.

Charging from ⅓ toward VCC, the capacitor reaches ⅔ after exactly ln 2 time constants — the remaining gap halves — and discharging from ⅔ toward zero it reaches ⅓ after ln 2 again. That is the 0.693 printed in the datasheet's Equations 1 to 3. The one-shot starts from an empty capacitor instead and stops at the same ⅔ threshold, which takes ln 3 = 1.0986 time constants; the datasheet rounds it to 1.1. This tool computes with the logarithms and shows the rounding for what it is: 0.02 % on the astable, 0.13 % on the one-shot, both invisible next to a capacitor's tolerance.

It also runs the equations backwards. Given a frequency and duty cycle it returns the resistor pair, snapped to E24, which is the question people actually arrive with.

555 astable frequency chart

The output frequency for the resistors and capacitors in the drawer, computed by the calculator above with R_A = R_B, which fixes the duty cycle at 66.7 % and makes the chart one-dimensional in each direction: ten times the resistor or ten times the capacitor is one tenth of the frequency. For a duty cycle nearer 50 % make R_B much larger than R_A, and read the frequency off the calculator instead.

C \ R_A = R_B	1 kΩ	4.7 kΩ	10 kΩ	47 kΩ	100 kΩ
1 nF	481 kHz	102 kHz	48.1 kHz	10.2 kHz	4.81 kHz
10 nF	48.1 kHz	10.2 kHz	4.81 kHz	1.02 kHz	481 Hz
100 nF	4.81 kHz	1.02 kHz	481 Hz	102 Hz	48.1 Hz
1 µF	481 Hz	102 Hz	48.1 Hz	10.2 Hz	4.81 Hz
10 µF	48.1 Hz	10.2 Hz	4.81 Hz	1.02 Hz	481 mHz

Worked example: a 3.9 kΩ, 3 kΩ and 10 nF astable

The defaults are the datasheet's own Figure 15 astable: R_A = 3.9 kΩ, R_B = 3 kΩ, C = 0.01 µF.

t_high = ln2 × (3.9k + 3k) × 10 nF      = 47.83 µs
t_low  = ln2 × 3k × 10 nF               = 20.79 µs
T      = ln2 × (3.9k + 6k) × 10 nF      = 68.62 µs   →  14.57 kHz
D      = 6.9k / 9.9k                    = 69.7 %

And the same equations run backwards, for 1 kHz at 60 % with 100 nF:

T      = 1 ms,  t_high = 600 µs,  t_low = 400 µs
R_B    = 400 µs / (ln2 × 100 nF)        = 5.77 kΩ   →  E24 5.6 kΩ
R_A    = 200 µs / (ln2 × 100 nF)        = 2.89 kΩ   →  E24 3.0 kΩ

Note what the E24 snapping costs: 5.6 kΩ and 3.0 kΩ give 1.02 kHz at 60.6 %, which is a better result than the capacitor's own ±10 % will deliver. Chasing exact resistors on a 555 is almost always effort spent in the wrong place.

Where the 555 timing equations stop being valid

The duty cycle of the classic astable is stuck above 50 %, and no choice of resistors escapes it: the capacitor charges through R_A and R_B in series but discharges through R_B alone, so the high phase is always the longer one. The tool refuses to design for 50 % or below rather than handing back a negative resistor. The usual escape is a diode across R_B so the charge path bypasses it, which buys duty cycles below half at the cost of putting a diode drop in the timing — the equations above no longer apply to it.

The resistor range matters more than it looks. The datasheet specifies its timing error with R_A between 1 kΩ and 100 kΩ. Go far below and the discharge transistor's own saturation becomes part of the timing; go far above and leakage at the threshold pin does. The tool flags the range rather than pretending the specification follows you out of it.

A bipolar 555 also has a habit that no equation shows: the output stage crowbars several tens of milliamps through the supply on every edge. That current is why a 555 needs real decoupling right at the chip and why it is a notorious noise source next to analogue circuitry — seewhy 100 nF for what that capacitor is doing, and prefer a CMOS variant (LMC555, TLC555) when the board has anything sensitive on it.

Common 555 timer mistakes

Expecting 50 % duty from the standard circuit. It cannot; it can only approach it as R_A shrinks toward zero, which the discharge transistor will not enjoy.
Precision resistors with an electrolytic timing capacitor. The capacitor's ±20 % swamps everything, and its leakage and temperature coefficient do the rest. Film or C0G where timing matters.
Assuming the frequency moves with the supply. It does not — that is the 555's best trick, since thresholds and charging voltage scale together. What does move with supply is the output current, and therefore the noise.
Retriggering a one-shot early. A monostable ignores triggers while its output is high; a trigger held low past the end of the pulse holds the output high too.
Leaving pin 5 (control) floating on a noisy board. A 10 nF to ground there keeps supply noise off the thresholds, which is exactly where it would turn into jitter.