PWM to voltage calculator

A PWM pin and a low-pass filter make a cheap digital-to-analog converter. This works out the DC level the output settles to, the ripple the filter leaves on it in volts and in LSBs of an N-bit converter, the corner frequency and settling time that ripple costs, and, run the other way, the capacitance that holds the ripple to a target, following TI's application note on using PWM as a DAC.

Fig 1 — 100 kHz PWM at D = 50 % between 0.00 V and 3.30 V through a first-order RC: the output settles to 1.65 V with 511 mV of ripple peak-to-peak, 159 LSB at 10 bits. Below, the same output with the ripple magnified ×3.5.

Solve for

Filter

PWM frequency f_PWM (kHz)

Duty cycle D (%)

High level V_H (V)

Low level V_L (V)

Resistance R (kΩ)

Capacitance C (nF)

Resolution N (bits)

Settle within (± LSB)

Timer clock f_clk (0 to skip) (MHz)

High-resolution edge bits (bits)

DC output V_DC: 1.65 V · 50 % of 3.30 V
1 LSB at 10 bits: 3.22 mV
Ripple at D = 50 %, peak-to-peak: 511 mV · 159 LSB
First harmonic at f_PWM · filter gain there: 2.10 V peak · 0.0990 (−20.1 dB)
−3 dB bandwidth, the DAC's bandwidth: 9.95 kHz · τ = 16.0 µs
Full-scale step: rise 10–90 %: 35.2 µs
Settling to ±0.5 LSB · to 1 %: 122 µs · 73.7 µs
Duty-cycle step: 3.30 mV · 1000 counts, 9.97 bits
Resolution: ripple alone · with the duty step (Eq 6): 2.69 bits · 2.68 bits

A single RC rolls off at 20 dB per decade, which SPRAA88 calls "sluggish": every tenfold cut in ripple costs a tenfold longer settling time. A second-order filter, or a higher PWM frequency, buys ripple back without that trade.

The ripple, ±256 mV, is wider than the ±0.5 LSB settling band, so the output never settles into it: the settling time is for the average, and the ripple rides on top.

How this is calculated

Standard: TI SPRAA88A — Using PWM Output as a Digital-to-Analog Converter on a TMS320F280x Digital Signal Controller (Sections 2 to 4, Eq 5 to 12, and Appendix A)

$V_{DC} = V_L + D\,(V_H - V_L), \qquad A_n = \frac{K}{n\pi}\left[\sin(n\pi D) - \sin\!\left(2n\pi\left(1 - \tfrac{D}{2}\right)\right)\right] = \frac{2K}{n\pi}\sin(n\pi D)$: SPRAA88 Eq 5, with the duty cycle p written D and K = V_H − V_L. "The D.C. component A0 is seen equal to the PWM amplitude multiplied by the PWM duty cycle"; the low level is added because the filter is linear. The harmonics A_n sit at whole multiples of f_PWM. Appendix A shows the first is largest at 50 % duty, which is why the resolution figures here, like the note's simulations, use the ripple at 50 %.
$\frac{V_{out}(s)}{V_{in}(s)} = \frac{1}{\tau s + 1}, \qquad \tau = RC, \qquad f_{-3\,dB} = \frac{1}{2\pi RC}$: Eq 7 and 8: the first-order section, whose bandwidth is "BW = 1/RC (rad/s)". The note calls its 20 dB per decade of roll-off "sluggish".
$\frac{V_{out}(s)}{V_{in}(s)} = \frac{\omega_n^2}{s^2 + 2\zeta\omega_n s + \omega_n^2}, \qquad BW = \omega_n\left[(1 - 2\zeta^2) + \sqrt{4\zeta^4 - 4\zeta^2 + 2}\right]^{1/2}$: Eq 9 and 10: the second-order filter, 40 dB per decade, with its −3 dB bandwidth in rad/s. At ζ = 0.707 the bandwidth equals ω_n.
$\text{two RC sections:}\quad \omega_n = \frac{1}{\sqrt{R_1R_2C_1C_2}}, \qquad \zeta = \frac{R_1C_1 + R_1C_2 + R_2C_2}{2\sqrt{R_1R_2C_1C_2}}$: Eq 11. The note: "the 2nd-order passive RC filter is unable to realize damping ratios less than 1." With both sections at the same time constant, ζ = 1 + R1/(2R2): 1.5 for identical sections, 1.05 with R2 = 10·R1.
$\text{series } R\text{–}L,\ \text{shunt } C:\quad \omega_n = \frac{1}{\sqrt{LC}}, \qquad \zeta = \frac{R}{2}\sqrt{\frac{C}{L}}$: Eq 12, the filter SPRAA88 built: 91 Ω, 100 µH and 22 nF give ω_n = 674200 rad/s (107.3 kHz) and ζ = 0.675. R includes the pin's own output resistance.
$\Delta V_{pp} = K\,\frac{\left(1 - e^{-DT/\tau}\right)\left(1 - e^{-(1-D)T/\tau}\right)}{1 - e^{-T/\tau}} \;\approx\; K\,D(1 - D)\,\frac{T}{\tau} \quad (T \ll \tau)$: First-order ripple, derived rather than quoted: the capacitor charging law applied to the on-time and the off-time, solved for the voltage that repeats every period T = 1/f_PWM. SPRAA88 gives no closed form — quantifying the ripple analytically is "considerably more difficult (if not impossible) due to the infinite summation in equation (1)" — and simulates instead. The second-order ripple here is that simulation done exactly: the periodic steady state of the filter's state equations, which reproduces the note's Figures 10 to 15 to within the reading of the plots.
$\Delta V_{pp} \approx 2A_1\,|H(j\omega_{PWM})|, \qquad |H| = \frac{1}{\sqrt{(1 - r^2)^2 + (2\zeta r)^2}}, \quad r = \frac{2\pi f_{PWM}}{\omega_n}$: The first harmonic through Eq 9, shown in the results as a check. For a second-order filter well below f_PWM it is nearly the whole ripple; higher harmonics fall as 1/n² in energy, per the note, and are attenuated harder still.
$1\,\text{LSB} = \frac{V_H - V_L}{2^N}, \qquad \Delta V_{step} = \frac{V_H - V_L}{(f_{clk}/f_{PWM})\,2^{b}}, \qquad \text{bits} = \log_2\frac{V_H - V_L}{\Delta V_{pp} + \Delta V_{step}}$: Eq 6: "total uncertainty = harmonic ripple + duty cycle resolution". The duty step is the swing over the counts in one period, b extra bits for a high-resolution timer: Section 3's example, 100 kHz from a 100 MHz clock, is 1000 counts and 3.3 mV steps on 3.3 V, "just less than 10-bit resolution".
$t_s = \tau\,\ln\frac{1}{\varepsilon}, \qquad \varepsilon = \frac{\text{settling band in LSB}}{2^N}$: Settling of a full-scale step, first order, from the charging law: to ½ LSB of N bits it is (N + 1)·ln 2·τ. For the second-order filters the time is found from the step response of Eq 9 as the last moment the error exceeds the band; for the Section 6 filter that gives a 10–90 % rise of 3.04 µs, the note's simulated figure.

Assumptions

An ideal square wave: instantaneous edges between exact V_H and V_L. The DC output is proportional to V_H − V_L, so the rail the pin runs from is the converter's reference, and its tolerance and noise pass straight through.
R includes everything in series with the pin, including the pin's own output resistance. SPRAA88 measured roughly 61 Ω on its part.
Nothing loads the filter output. SPRAA88 suggests a voltage follower after the filter; a resistive load forms a divider with R and lowers the DC level, which this calculation does not include.
Ideal components: no capacitor ESR or inductor resistance, and no self-resonance. The note accepts this for its RLC filter: "it is not important in the PWM/DAC application to build a filter with exact bandwidth."
Ripple is the steady state for a constant duty cycle. The resolution in bits uses the ripple at 50 % duty, the worst case, as SPRAA88's simulations do.
The duty step assumes f_clk/f_PWM counts per period over the whole range. Timer limits near 0 % and 100 % duty, such as the HRPWM range limitation in SPRAA88 Section 7.1, are not modelled.
The capacitance search holds the ripple at 50 % duty to the target. Two RC sections are given the same time constant, C2 = C1·R1/R2; the RLC keeps L and R and varies C.

What sets the voltage and the ripple of a filtered PWM output

A PWM output is a square wave between two levels, and TI's application note SPRAA88 starts from the observation that it can be split into two parts: a DC component, and a second square wave of the same duty cycle whose average is zero. Its Fourier analysis (Eq 5) gives the DC part directly: "The D.C. component A0 is seen equal to the PWM amplitude multiplied by the PWM duty cycle. This is the desired D/A output." A 3.3 V pin at 50 % duty is 1.65 V of DC; at 25 %, 0.825 V. Everything else in the wave is harmonics, and they "exist at integer multiples of the PWM carrier frequency": 100 kHz PWM puts them at 100 kHz, 200 kHz, 300 kHz and on up.

A low-pass filter keeps the DC and removes the harmonics, and how well it does that is the whole design. The note is plain about why neither extreme works: "Use a filter with too low a cut-off frequency, and DAC bandwidth suffers. Use a filter with too high a cut-off frequency or with slow stop-band rolloff, and DAC resolution suffers." The filter's bandwidth is the bandwidth of the converter, since the duty cycle can only be changed as fast as the filter lets the output follow; its roll-off above the corner decides how much of the harmonic content survives as ripple. SPRAA88 puts the roll-off at 20 dB per decade per order, so a single RC section passes a tenth of the amplitude of a harmonic a decade above its corner, and a second-order filter a hundredth.

Which harmonic matters depends on the duty cycle. Appendix A of the note shows the first harmonic, at the PWM frequency itself, carries the most energy at 50 % duty, and that "the energy in higher harmonics decreases as a function of 1/n² regardless of the duty cycle". The first harmonic is also the one a low-pass filter attenuates least, so it sets the ripple, and 50 % is the worst case. The calculator reports the ripple at the duty cycle entered and at 50 %, and measures the resolution against the 50 % figure.

The ripple itself has no simple formula for a real filter; the note says quantifying it analytically is "considerably more difficult (if not impossible) due to the infinite summation" of harmonics, and it runs a simulation instead. The calculator does the same simulation exactly. It writes each filter as its state equations, finds the output that repeats from one PWM period to the next, and takes its peak-to-peak swing. For a single RC section this reduces to the capacitor charging law applied to the on-time and the off-time in turn, the formula in the reference note above; for the two second-order filters there is no shortcut, and the periodic solution is computed directly. The results reproduce the resolution curves SPRAA88 plots in its Figures 10 to 15 as closely as the plots can be read.

Ripple is only half of the error. The duty cycle is set by a counter, and a counter running at f_clk has only f_clk/f_PWM positions per period to put the edge in. SPRAA88's example is 100 kHz PWM from a 100 MHz clock: "1000 clock counts per cycle", steps of 3.3 mV on a 3.3 V swing, "just less than 10-bit resolution". Raising the PWM frequency moves the harmonics further above the filter corner and cuts the ripple, but it divides the counts, so the steps grow. The note adds the two, "total uncertainty = harmonic ripple + duty cycle resolution", and concludes that "the optimal carrier frequency is the one where the total uncertainty is smallest". Enter the timer clock and the calculator reports both terms and the resolution they leave together.

RC filter values for 8-, 10- and 12-bit ripple

The −3 dB corner a filter needs to hold the ripple to ½ LSB at 50 % duty, found by the calculator's capacitance search at each PWM frequency, and the time that filter takes to settle a full-scale step to ½ LSB at 10 bits. The corner does not depend on the supply or on the resistor chosen; pick R, and C follows from the corner. Only the ratio of ripple to swing matters, which is what an LSB is.

One RC section

f_PWM	8-bit corner	10-bit corner	12-bit corner	10-bit settling
1.00 kHz	1.24 Hz	311 mHz	77.7 mHz	3.90 s
10.0 kHz	12.4 Hz	3.11 Hz	777 mHz	390 ms
20.0 kHz	24.9 Hz	6.22 Hz	1.55 Hz	195 ms
50.0 kHz	62.2 Hz	15.5 Hz	3.89 Hz	78.1 ms
100 kHz	124 Hz	31.1 Hz	7.77 Hz	39.0 ms
1.00 MHz	1.24 kHz	311 Hz	77.7 Hz	3.90 ms

Two RC sections, R2 = 10·R1, equal time constants

f_PWM	8-bit corner	10-bit corner	12-bit corner	10-bit settling
1.00 kHz	23.9 Hz	12.0 Hz	5.98 Hz	91.9 ms
10.0 kHz	239 Hz	120 Hz	59.8 Hz	9.19 ms
20.0 kHz	478 Hz	239 Hz	120 Hz	4.59 ms
50.0 kHz	1.20 kHz	598 Hz	299 Hz	1.84 ms
100 kHz	2.39 kHz	1.20 kHz	598 Hz	919 µs
1.00 MHz	23.9 kHz	12.0 kHz	5.98 kHz	91.9 µs

The first table is the argument against a single RC section. Each extra two bits of ripple cost a factor of four in corner frequency, and more than that in settling time because the band it settles into narrows too, since the section's attenuation is only proportional to frequency: 12 bits at 20 kHz needs a corner of 1.55 Hz and923 ms to settle to ½ LSB. The second section changes the arithmetic. Its attenuation grows with the square of frequency, so two more bits cost only a factor of two in the corner, and across the tables the two-section filter's corner is 19 to77 times higher for the same ripple. That, not the extra resistor and capacitor, is the real price of a single section.

Read the rows the other way, too. For a fixed filter, ten times the PWM frequency buys ten times less ripple from one RC section and a hundred times less from two; it is the cheapest improvement available, until the duty-cycle step catches up with it.

Worked example: SPRAA88's 10 kHz RC at 100 kHz, then the RLC it built

The calculator's defaults are the note's numbers: a 3.3 V output at 100 kHz from a 100 MHz clock, the Section 3 example, into Table 1's Filter #1, a first-order section with a 10 kHz bandwidth, built here from 1.6 kΩ and 10 nF. Resolution is measured at 10 bits, since that is roughly what the counter can deliver.

1 LSB at 10 bits     3.3 V / 1024                        = 3.22 mV
DC at 50 %           0.5 × 3.3 V                         = 1.65 V
corner               1.6 kΩ, 10 nF, τ = 16.0 µs         = 9.95 kHz
first harmonic       2.10 V peak at 100 kHz, gain 0.099
ripple at 50 %       peak-to-peak                        = 511 mV   (159 LSB)
duty step            3.3 V / 1000 counts                 = 3.30 mV   (9.97 bits)
resolution           ripple alone 2.69 bits, with the step 2.68 bits
settling to ½ LSB    11 × ln 2 × τ                       = 122 µs

Half a volt of ripple on a 1.65 V output: the filter leaves2.69 bits of a converter whose counter could manage nearly ten. SPRAA88's Figure 10 shows the same thing, every curve for Filter #1 starting from about 2.7 bits at 100 kHz. The first harmonic alone accounts for 416 mV of the511 mV; the rest is the third and fifth harmonics, which a corner only a decade below the PWM frequency barely touches. Moving the duty cycle does not rescue it. At the 15.2 % that gives 0.5 V, the low peak of the note's test sine wave, the ripple is still 264 mV.

There are three ways out, and the calculator shows each. Keep one section and lower its corner until the ripple is ½ LSB: the capacitance search puts C at 3.20 µF with the same 1.6 kΩ, a corner of31.1 Hz, and 39.0 ms to settle. Or add a second section, 16 kΩ with 5.00 nF behind 1.6 kΩ with50.0 nF: the same ½ LSB with a corner of 1.20 kHz, settling in 919 µs, 42 times faster. Even the two-section filter with the original values, 1.6 kΩ and 10 nF then 16 kΩ and 1 nF, cuts the ripple from 511 mV to40.0 mV at a 5.98 kHz corner.

The third is the note's own answer: a second-order RLC filter and a much higher PWM frequency. Section 6 builds Filter #5 from "R = 91 Ω L = 100 µH C = 0.022 µF" and runs it at 5 MHz, chosen from Figure 14 as the frequency that "gives the best D/A resolution for Filter #5 using hi-resolution PWM at 100 MHz CPU clock". Select the RLC filter, set the PWM frequency to 5000 kHz and the edge bits to 6:

Eq 12                ω_n = 1/√(100 µH × 22 nF)           = 674200 rad/s (107 kHz)
                     ζ = (91/2) × √(22 nF / 100 µH)      = 0.675
bandwidth (Eq 10)                                        = 112 kHz
ripple at 50 %       gain 4.61e-4 at 5 MHz          = 1.88 mV   (0.58 LSB)
duty step            20 counts × 2⁶                      = 2.58 mV
resolution (Eq 6)                                        = 9.53 bits   (no HRPWM: 4.31 bits)
rise, 10–90 %                                            = 3.04 µs
settling to 1 %  ·  to ½ LSB                             = 9.67 µs  ·  16.1 µs

The note reports the same filter as "ωn = 674200 rad/s (107.3kHz) and ζ = 0.675", a simulated 10–90 % rise of "3.04 µsec", and a measured "combined rise and settling time from 0% to ~100%" of "roughly 10 µsec", which is the 1 % settling time above. Its Figure 14 peaks at about 9.6 bits for the nominal Filter #5; the as-built values give9.53. Against the RC example this is11 times the bandwidth and6.9 more bits, and it needs the fast clock: at 5 MHz an ordinary 100 MHz counter has 20 positions per period, and without the six high-resolution bits the duty step, not the ripple, limits the converter to 4.31 bits. The original 10 kHz RC at 5 MHz would manage 8.00 bits, still limited by its ripple.

Where the PWM filter model stops being valid

The rail is the reference. Eq 5 makes the DC output proportional to the amplitude of the wave, so the supply the pin runs from is the converter's voltage reference. Its tolerance is a gain error, and its noise and ripple reach the output scaled by the duty cycle, unfiltered by anything the calculator models. A PWM DAC is only as accurate as the rail behind the pin.

The pin has resistance. SPRAA88's footnote to Section 6: "The PWM pin output impedance was seen to be roughly 61 Ω such that a 30 Ω resistor was used to construct the actual low-pass filter circuit." With kilohm resistors the pin barely matters; in an RLC filter it is two-thirds of the resistance that sets the damping, and anything that changes the pin's resistance changes ζ with it.

Nothing may load the output. The note's answer to the passive filter's sensitivity to "upstream or downstream impedances" is a voltage follower after it, where "an op-amp with large gain bandwidth is not needed" because the harmonics are already gone. Without one, a resistive load forms a divider with the filter resistor and lowers the DC level, and an unbuffered ADC input draws charge from the filter capacitor at every conversion. Neither is in the calculation.

The ends of the range. The duty step assumes every count is usable. SPRAA88 Section 7.1 shows otherwise for its part: "the HRPWM output reverts to that of standard PWM during the first three and the last two SYSCLKOUT cycles of the PWM period", which at 5 MHz loses the fine resolution above 85 % and below 10 % of full scale. Check the timer's own limits near 0 % and 100 % before relying on the ends of the range.

Offset and gain. The note found "a small amount of offset error" in its output and calibrated it out with the on-chip ADC, observing that "it is unlikely that significant gain error would exist since the presented PWM/DAC contains no analog amplifiers". Real edges are not instantaneous, and a difference between the rise and fall times shifts the average slightly; a buffer amplifier adds its own offset and gain error. The calculator gives the ideal DC level.

Real components. Capacitor ESR, inductor winding resistance and self-resonance are not modelled. SPRAA88 notes inductors' "deviation from the ideal mathematical model", and also that "it is not important in the PWM/DAC application to build a filter with exact bandwidth"; the ripple at 5 MHz, though, depends on the capacitor still being a capacitor there. For an active filter the op-amp's gain bandwidth is the limit, which the note wants "at least 5 to 10 times greater than the highest expected input frequency"; at PWM frequencies above 1 MHz it finds such op-amps "relatively expensive", which is why its filters are passive.

Common PWM to voltage mistakes

Putting the corner a decade below the PWM frequency and expecting a clean output. A single section is then only 20 dB down at the first harmonic, which is the worked example: 159 LSB of ripple at 10 bits. The first table shows how far below the PWM frequency the corner really has to go.
Checking the ripple at the duty cycle the scope happened to show. The first harmonic peaks at 50 %, so a filter checked at 10 % or 90 % will disappoint mid-scale. Size for 50 %.
Cascading two identical RC sections and expecting the corner of one. The second section loads the first; Eq 11 gives ζ = 1.5 and Eq 10 a bandwidth of 0.374/RC, well under half the single section's 1/RC. A second resistor ten times the first comes much closer to two independent sections.
Filtering an 8-bit counter and expecting 12 bits. The filter can only average between the duty cycles the counter can set; below the duty-cycle step, more filtering buys nothing. That is the second term of Eq 6, and the reason SPRAA88's results depend on the high-resolution timer.
Raising the PWM frequency to cut ripple without checking the counts. The ripple falls and the step grows; past the optimum of Eq 6 the resolution falls again. The note's curves all have that peak.
Forgetting the settling time. A filter that holds ripple to ½ LSB is also slow to follow the duty cycle, and a control loop or a waveform generator built on it inherits the delay. The phase lag of higher-order filters matters too, which SPRAA88 flags for closed-loop control.
Reading the filter output with a low-impedance load: a meter on a low range, an ADC without a buffer, a transistor base. The DC level is only V_L + D(V_H − V_L) into a high impedance.