Crystal load capacitor calculator

A crystal is trimmed to run on-frequency into one specific load. The two capacitors on the MCU pins have to present that load, after the stray capacitance of the pins and traces is counted. Get it wrong and the oscillator still starts — just off frequency, and your RTC drifts.

Fig 1 — Pierce oscillator; the crystal sees C_L = 12.5 pF.

Rated load capacitance C_L (pF)

Stray capacitance per side (pF)

Frequency (MHz)

Shunt capacitance C0 (0 to skip) (pF)

Motional capacitance C_m (0 to skip) (fF)

Max ESR (0 to skip) (Ω)

Oscillator gm (0 to skip) (mA/V)

Swing at crystal (0 to skip) (Vpp)

Max drive level (0 to skip) (µW)

C1 = C2, exact: 22.0 pF
Nearest E12 value: 22 pF
Load seen with 22 pF: 12.50 pF (-0.00 pF)

How this is calculated

Standard: TI SWRA372 (AN-100) Section 4, Eq. 1 — load capacitance; ST AN2867 Sections 3.3–3.5 — gain margin and drive level

$C_L = \frac{(C_1 + C_s) \cdot (C_2 + C_s)}{C_1 + C_2 + 2 \cdot C_s}$: SWRA372’s per-side convention: C_s is counted once on each leg. Documents that lump the stray into a single term (AN2867 among them) solve to C1 = 2·(C_L − C_s) instead — same physics, different definition of C_s.
$C_1 = C_2 = 2 \cdot C_L - C_s$: Symmetric pair, per-side stray.
$\frac{df}{dC_L} = \frac{-f \cdot C_m}{2 \cdot (C_0 + C_L)^2}$: Frequency pulling at C_L.
$\text{gm}_{crit} = 4 \cdot \text{ESR} \cdot (2\pi f)^2 \cdot (C_0 + C_L)^2$: Gain margin is gm divided by gm_crit, and it needs to be greater than 5.
$\text{DL} = \frac{\text{ESR} \cdot \bigl(\pi \cdot f \cdot (C_0 + C_L) \cdot V_{pp}\bigr)^2}{2}$: Drive level.

Assumptions

Symmetric pair: C1 = C2. Asymmetric values are occasionally used to trim, but the crystal only sees their series combination.
Stray capacitance per side is an estimate — MCU pin (2-4 pF, from the datasheet) plus pad and trace (1-2 pF). Measure it with a frequency counter if the application cares about ppm.
Nearest E12 value is chosen; ±5 % C0G/NP0 parts are assumed. X7R changes with voltage and temperature and should not be used here.
Gain margin uses the maximum ESR from the datasheet and the MCU's oscillator gm; AN2867 asks for a margin above 5. Drive level uses the swing you enter, which is roughly V_DD for a rail-to-rail inverter.
Pulling figure is a small-signal estimate around C_L and needs C_m and C0 from the crystal datasheet.

What sets a crystal's load capacitors

A crystal is trimmed at the factory to sit on its nominal frequency when it sees one specific capacitance across its terminals: the rated load C_L, printed on the datasheet as 8, 9, 12.5, 18 or 20 pF. In a Pierce oscillator the crystal sees the two pin capacitors in series, and on each side the pin, pad and trace stray capacitance sits in parallel with the capacitor you fitted. That load, and the equal-capacitor case solved for the part to fit, are the first two expressions under How this is calculated above.

C_s is the stray per side. The MCU datasheet gives the pin capacitance (2 to 4 pF is normal); a short trace and its pad add another 1 to 2 pF. This per-side form is Equation 1 of TI SWRA372, section 4, and it is a convention worth noticing: ST AN2867, Oscillator design guide for STM8 and STM32 instead lumps the whole stray into one term, which solves to C1 = 2·(C_L − C_s) — a full E12 step lower for the same numbers. Neither is wrong; they define C_s differently. The calculator follows SWRA372's per-side definition, rounds C to the nearest E12 value and then reports the load you actually get with that part.

Two more checks from AN2867 decide whether the oscillator starts at all, and the tool runs both when you supply ESR, C₀ and the MCU's transconductance. Gain margin (§3.3) is the critical transconductance expression above, with the margin being gm divided by it. Drive level (§3.5) is the last expression, whose bracketed term is the peak current π·f·(C₀+C_L)·V_pp through the crystal; compare the result against the part's rated drive, typically 100 µW for an MHz-class crystal and 0.5 to 1 µW for a tuning fork.

Frequency pulling is the last output. With C_m and C₀ from the crystal datasheet, the slope of frequency against load at the rated C_L is the pulling expression above. It is in hertz per farad; the tool reports the more usable Hz/pF.

Crystal load capacitor chart

Each external capacitor for the load capacitances crystals are actually sold with, computed by the calculator above for a symmetric pair: C1 = C2 = 2·C_L − C_stray, then the E12 value nearest it, and the load that real part presents once the stray is added back. The stray is per side, the MCU pin plus its pad and trace, and the two columns bracket the range it usually falls in.

C_L	Exact, 3 pF stray	E12 part	Load it gives	Exact, 5 pF stray	E12 part	Load it gives
8 pF	13 pF	12 pF	7.5 pF	11 pF	12 pF	8.5 pF
9 pF	15 pF	15 pF	9 pF	13 pF	12 pF	8.5 pF
10 pF	17 pF	18 pF	10.5 pF	15 pF	15 pF	10 pF
12 pF	21 pF	22 pF	12.5 pF	19 pF	18 pF	11.5 pF
12.5 pF	22 pF	22 pF	12.5 pF	20 pF	22 pF	13.5 pF
15 pF	27 pF	27 pF	15 pF	25 pF	27 pF	16 pF
18 pF	33 pF	33 pF	18 pF	31 pF	33 pF	19 pF
20 pF	37 pF	39 pF	21 pF	35 pF	33 pF	19 pF
22 pF	41 pF	39 pF	21 pF	39 pF	39 pF	22 pF

The chart is why the stray matters more than the datasheet suggests: at the 8 pF and 9 pF loads that low-power parts specify, 2 pF of extra stray is a fifth of the external capacitor, and the E12 grid is coarse enough at those values that the rounding alone can move the load by half a picofarad or more.

Worked example: an 8 MHz crystal with a 10 pF load

8 MHz crystal, C_L = 10 pF, ESR 80 Ω, C₀ = 5 pF, C_m = 20 fF. Stray per side estimated at 3 pF. MCU HSE transconductance 25 mA/V.

C  = 2 × 10 − 3 = 17 pF          nearest E12: 18 pF (15 is further)

Load with 18 pF:
  C_L' = (18 + 3) / 2 = 10.5 pF          error +0.5 pF

Pulling slope:
  df/dC = 8e6 × 20e-15 / (2 × (5e-12 + 10e-12)²)
        = 1.6e-7 / (2 × 2.25e-22)
        = 3.56e14 Hz/F  =  356 Hz/pF
  Δf    = 356 × 0.5 = 178 Hz  →  178 / 8e6 = 22 ppm

Gain margin:
  (2π × 8e6)²        = 2.527e15
  (C0 + C_L)²        = (15e-12)² = 2.25e-22
  gm_crit = 4 × 80 × 2.527e15 × 2.25e-22 = 1.82e-4 A/V = 0.182 mA/V
  margin  = 25 / 0.182 = 137                    (> 5, starts with room to spare)

Drive level, 1.0 V pk-pk measured at the crystal:
  I_pk = π × 8e6 × 15e-12 × 1.0 = 377 µA
  DL   = 80 × (377e-6)² / 2    = 5.7 µW          (rated 100 µW, fine)

The calculator reports 17.0 pF exact, 18 pF E12, 10.50 pF seen, +0.50 pF error, 356 Hz/pF and 22.2 ppm. The extra half picofarad of load pulls the crystal 22 ppm below nominal, which is already the whole tolerance budget on many parts. 15 pF would land at 9.0 pF and −1.0 pF the other way; fitting one 15 and one 18 gets within 0.25 pF, and that is the one case where an asymmetric pair earns its keep.

Where the load capacitance model stops being valid

32.768 kHz is a different animal. The formulas are the same; the numbers are not. A tuning-fork crystal has an ESR of 35 to 90 kΩ, a C₀ around 1.3 pF and a drive rating of 0.5 to 1 µW. Run the gain-margin check on a 70 kΩ, 12.5 pF part and gm_crit comes out around 2.3 µA/V. A low-power LSE driver offers only a few µA/V, so the same MCU that has a margin of 137 on its HSE can be at 2 on its LSE and fail to start cold. Drop to a 6 or 7 pF crystal, or turn the driver strength up one step and accept the extra hundred nanoamps. Conversely a driver set too strong overdrives the fork and ages it; the frequency walks.

Why RTC crystals drift anyway. A tuning fork's temperature curve is a parabola centred at 25 °C, about −0.035 ppm/°C². At 0 °C it is 22 ppm low; at −20 °C, 71 ppm, which is six seconds a day. No load capacitor fixes that; you need temperature compensation in firmware or a TCXO. The load error on top of it is what this tool controls, and at 32 kHz the sensitivity is worse because C₀ is so small: the same 0.5 pF error is typically 15 to 25 ppm. Thecrystal ppm calculator adds that parabola, the initial tolerance and ageing together into a total drift budget.

The gain-margin formula is conservative. AN2867 derives it for the crystal's own C₀ plus C_L; a probe on the pin adds its own capacitance to both the load and the drive calculation, so measure V_pp with a sub-1 pF active probe or accept that the measurement itself moves the number. Margins between 3 and 5 often start fine on the bench and fail at −40 °C or on a part from a different lot. Any series R_ext on the driver output adds to ESR.Why the crystal won't start walks through the rest of the failure modes, in the order worth checking them.

Measuring the stray instead of guessing. Fit the calculated capacitors, run the oscillator, and read the frequency on a counter through a buffered output (MCO pin, not a probe on the crystal). Convert the error back to capacitance with the pulling slope. In the example, 356 Hz/pF is 44 ppm/pF, so a measured −20 ppm means the crystal sees 0.45 pF more load than assumed, which is 0.9 pF more stray per side since C_L = (C + C_s)/2. Rerun the tool with C_s = 3.9 pF and pick again. One iteration is enough.

Common crystal load capacitor mistakes

Fitting C1 = C2 = C_L. Two 12.5 pF caps in series are 6.25 pF, plus stray gives about 9 pF, and the crystal runs 100 ppm or more high. The external value is roughly twice C_L, less stray.
Copying the reference-design values onto a different layout. Those 20 pF parts were chosen for that board's stray and that crystal's C_L. Change either and the number changes.
Using X7R or X5R. Their capacitance moves 15 % over temperature and more with voltage. Load capacitors are C0G/NP0 only, ±5 % or better.
Ignoring drive level on a tuning fork. 1 µW is very little; an HSE-class driver, or a strong LSE setting, blows straight past it and the crystal ages several ppm a year. Check it, and add R_ext if needed.
Long traces or a via to the crystal, or a ground pour under it with no guard. The stray is no longer 3 pF and it is not the same on both sides. Keep the crystal within a few millimetres of the pins; AVR186 has the layout rules.