Exposed pad stencil and thermal via calculator

The thermal pad under a QFN, SON or PowerPAD is the die pad of the lead frame, and it has to be soldered — for the heat path and, SLUA271 says, for mechanical strength even when the heat does not matter. It cannot simply be printed full: a 1:1 aperture floats the part on the paste and opens the lead fingers, so the stencil is windowed to 50–70 % of the pad, each window sized so the paste releases, over an array of 0.3 mm vias on a 1 mm pitch that carry the heat down and the excess solder with it. Enter the pad, the window grid, the stencil and the vias to get the window size and web, the paste volume, the IPC-7525 ratios, the via count, and what the voiding you expect will cost in θ_JA.

Fig 1 — The 5 × 5 mm thermal pad to scale, with the 2 × 2 stencil windows that print 60 % of it in paste and the 25 thermal vias on a 1 mm pitch. SLUA271: a 1:1 aperture "results in excessive metal volume that can 'float' the part"; the windows regulate the volume and let the paste out-gas.

Pad width (mm)

Pad height (mm)

Windows across

Windows down

Paste coverage (%)

Stencil thickness (mm)

Stencil

Via pitch (0 = none) (mm)

Via drill (mm)

Voiding after reflow (%)

Stencil windows: 2 × 2, each · web between: 1.94 × 1.94 mm · 0.56 × 0.56 mm
Paste coverage · volume · what 1:1 would print: 60 % · 1.88 mm³ · 3.13 mm³
Area ratio (IPC-7525, ≥ 0.66) · aspect ratio (> 1.5): 3.87 · 15.49
Thermal vias · share of the pad area: 25 × 0.3 mm · 7.1 %
Joint after 20 % voiding · θJA penalty (SNVA183): 80 % soldered · +1.6 %

How this is calculated

Standard: TI SLUA271; TI SNVA183; TI SLOA120

$a = \frac{W_{pad}}{n_x}\sqrt{\frac{c}{100}}, \qquad b = \frac{H_{pad}}{n_y}\sqrt{\frac{c}{100}}$: Window size for an n_x × n_y grid at coverage c %, each window centred in its cell. SLUA271 §4.4: 50–70 %.
$\text{area ratio} = \frac{a\,b}{2(a+b)\,T}, \qquad \text{aspect ratio} = \frac{\min(a,b)}{T}$: IPC-7525 via SLUA271 figure 4-2: ≥ 0.66 for laser-cut stencils, 0.57 for nickel-formed; aspect > 1.5.
$V_{paste} = W_{pad} H_{pad}\,\frac{c}{100}\,T$: Printed volume against the 1:1 volume that "can float the part".
$N_{via} = \left(\left\lfloor\frac{W_{pad} - d}{p}\right\rfloor + 1\right)\left(\left\lfloor\frac{H_{pad} - d}{p}\right\rfloor + 1\right)$: Vias of drill d on pitch p that fit inside the pad. SLUA271 §3.4.1 and SLOA120: 1.0 mm and 0.3 mm.
$\Delta\theta_{JA}(\text{coverage}) : 50\% \to +4\%,\ 20\% \to +13\%,\ 10\% \to +19\%,\ 5\% \to +34\%$: SNVA183 figure 12(a), interpolated linearly; coverage taken as 100 % minus the voiding entered.

Assumptions

Windows are equal, centred in equal cells; SLUA271's figure 4-3 pattern.
Paste reflows to wet the whole pad, so voiding is the only loss of coverage; solder drained into open vias is not modelled.
The via array is a rectangular grid centred on the pad, with whole vias only.
SNVA183's coverage table is a simulation of an e-TSSOP on a four-layer JEDEC board; other packages have different critical points.
Lead-finger apertures are not computed; SLUA271's example (0.23 × 0.8 mm in 0.125 mm) is the check on the ratio formulas.

What sets how an exposed pad is soldered

The pad on the underside of a QFN, SON or PowerPAD is the package's lead-frame die pad, left bare: "the lead frame die pad (or thermal pad) is exposed on the bottom of the IC", SLOA120 says, and "this provides an extremely low thermal resistance (θ_JC) path between the die and the exterior of the package". It is worth nothing until it is joined to copper. SLUA271: "to take full advantage of this feature, the pad must be physically connected to the PCB substrate with solder", and even where the power is low "the center thermal pad, however, should always be soldered to the board for mechanical strength and reliability". Thermal grease is not a substitute — the joint is solder, printed as paste through a stencil and reflowed — and SNVA183's model of what an unsoldered pad costs is the last row of the results.

Three numbers decide the print. Coverage: a stencil opening the full size of the pad "results in excessive metal volume that can 'float' the part and cause opens and other manufacturing defects", because the lead-finger joints beside it are only "0,050 mm to 0,075 mm" thick; SLUA271's figure 4-3 windows the pad so that "the solder-paste coverage is approximately 50 % to 70 % of the pad area", which "enables out-gassing of the solder paste during reflow and also regulates the finished solder thickness". Area ratio:each window has to release its paste, which IPC-7525 governs through the ratio of aperture area to aperture wall area — 0.66 and above for a laser-cut stencil, and "nickel-formed stencils print with area ratios down to 0.57". Vias: the pad's copper reaches the inner planes through an array "on a pitch of approximately 1,0 mm" of "0,3 mm diameter drill holes", which also drain paste; "a smaller via offers less risk of solder volume loss", and plugging or top-side tenting stops it.

Voiding is the outcome to check, on x-ray. SLUA271's limits: "the amount of voiding post reflow in the thermal pad solder joint should not exceed 50 % in high-power applications", and "25 % has been determined to be a point of diminishing thermal performance returns". SNVA183 simulated what coverage costs: "when solder coverage decreases to 50 %, 20 %, 10 % and 5 %, the thermal resistance θ_JA will increase by about 4 %, 13 %, 19 %, and 34 %, respectively", with 10 % "a critical point". The calculator reads the voiding entered as lost coverage and interpolates that table.

Worked example: a 5 mm pad, 2 × 2 windows, 25 vias

The defaults: a 5 × 5 mm pad, printed at 60 % through a 2 × 2 window in a 0.125 mm laser-cut stencil, with 0.3 mm vias on a 1 mm pitch, and 20 % voiding after reflow.

window          (5 mm / 2) × √0.60                  = 1.94 mm square, 0.56 mm web between
area ratio      1.94² / (4 × 1.94 × 0.125)          = 3.87       (≥ 0.66, fine)
aspect ratio    1.94 / 0.125                        = 15.5       (> 1.5)
paste           25 mm² × 0.60 × 0.125 mm            = 1.88 mm³   (1:1 would print 3.13 mm³)
vias            5 × 5 on a 1 mm pitch               = 25 × 0.3 mm, 7.1 % of the pad
joint           100 − 20 % voids                    = 80 % soldered → θJA +1.6 % (SNVA183)

SLUA271's own lead-finger example is the check on the ratios: a 0.23 × 0.8 mm aperture in the same 0.125 mm foil has an area ratio of 0.71 and an aspect ratio of 1.84, both just inside IPC-7525, which is why fine-pitch fingers are the parts that set the stencil thickness. Turn the pad's windows into a 4 × 4 array at 50 % and the apertures shrink to 0.88 mm with an area ratio of 1.77 — still fine on a 5 mm pad, but a 2 mm SON pad with the same 4 × 4 falls to 0.59, nickel-only.

Where the exposed-pad model stops being valid

The coverage table is one package on one board.SNVA183's percentages are a simulation of an e-TSSOP on a JEDEC four-layer board with the un-soldered area "underneath the middle of the exposed pad", and it notes "the critical point is dependent on the packages and boards. For example, for a 44L LLP on a 4L JEDEC board, the critical point is 20 %." Real voids are scattered, and θ_JA depends on the copper around the part as much as on the joint.
PowerPAD guidance differs on windowing. SLOA120, for PowerPAD parts, says "do not use cross hatching in the stencil thermal pad opening. This significantly reduces the amount of solder paste applied and increases voiding", and refers to the openings in each datasheet. SLUA271's windowed 50–70 % is for QFN and SON. Follow the datasheet's stencil drawing where it gives one.
Via count is a starting point, not a requirement."Not all applications require vias. The need for vias depends on the amount of power the device dissipates." How many actually help is thevia calculator's question.
Paste volume is not joint thickness. The printed volume includes flux that leaves during reflow, and some solder goes down the vias. The finished thickness is set by the lead fingers' standoff, which is why the pad is printed lighter than they are.
Process matters as much as geometry. SLUA271's trials found voiding rises with "an excessive soak time, which activates the majority of the flux before the melting temperature of the alloy", and falls with top-side via tenting; neither is in the calculator.

Common exposed-pad mistakes

Leaving the pad unsoldered because "it is only ground". SLUA271 wants it soldered regardless, for mechanical strength; SNVA183's model says a joint that has effectively no coverage is the 34 %-and-rising end of the curve.
Printing the pad 1:1. The part floats on the paste, the lead fingers open, and the excess runs down the vias. Window it.
Thermal grease on an exposed pad. It is a solder joint; grease is for a heatsink interface, and an ungreased-but-unsoldered pad is the previous mistake with extra steps.
Big vias, untented. Solder drains into 0.5 mm holes and the joint is left with the voids; 0.3 mm or smaller, plugged or tented from the top, or SLOA120's fallback of vias outside the pad.
Thermal-relief spokes on the pad's plane connection. SLOA120: "do not use a thermal relief web or spoke connection which impedes the conduction path into the inner copper layer(s)."
Pad copper larger than the package pad. SLUA271: equal to the exposed pad, with 0.2 mm of clearance to the lead-finger lands to prevent bridging.