What an IC's thermal pad is for, and how to solder it

The exposed pad on a QFN or PowerPAD is the die pad and the heat path out of the package, but only once it is soldered. Why the stencil prints 50–70 % of it.

The bare metal square on the underside of a QFN is not a heatsink and not a ground pin, though it usually ends up connected to ground. It is the die pad of the package’s lead frame — the copper the silicon is glued to — left uncovered by the moulding. TI’s PowerPAD note describes the construction in one sentence: “the lead frame die pad (or thermal pad) is exposed on the bottom of the IC”, and “this provides an extremely low thermal resistance (θ_JC) path between the die and the exterior of the package”. Everything the package can do thermally goes through that square, and it goes nowhere until the square is soldered to copper.

Which is the short answer to the question this article exists for. The pad is soldered, with solder paste through a windowed stencil, over an array of vias — and it is soldered even when the part runs cool, because TI’s QFN attachment note wants it “always” soldered “for mechanical strength and reliability”. Thermal grease belongs between a heatsink and a package top; put it on an exposed pad and the pad is simply unsoldered with extra steps. The exposed pad stencil calculator does the geometry; this article is what the three TI notes say and the numbers behind each rule.

Cross-section of a QFN on a circuit board. Inside the package, a silicon die sits on a thin die-attach layer on the copper lead-frame die pad; mould compound surrounds them and the pad is exposed at the base. The pad is soldered to a copper pad on the board, and five vias run from that pad down through the board to an inner copper plane. Arrows show heat flowing from the die through the die attach, the pad, the solder and the vias into the plane. — Fig 1 — SLOA120's section, redrawn: "the lead frame die pad (or thermal pad) is exposed on the bottom of the IC", giving "an extremely low thermal resistance (θJC) path between the die and the exterior of the package". Everything after that path is the board's: the solder joint, the pad copper, and the vias into the planes. An unsoldered pad breaks the chain at its first link.

What the pad is

A moulded package is a poor conductor of heat. The die sits on the lead frame’s central pad, attached with epoxy or film, and in a conventional package that pad is buried in mould compound; the heat leaves through the leads and the plastic, and θ_JA is tens of degrees per watt. Exposing the pad at the base changes the path: die, die attach, copper pad, and out. SNVA183 groups these as packages “having very low thermal resistance between junction-to-case”, and SLOA120’s point is that the package is “designed to eliminate the use of bulky heat sinks and slugs” by handing the heat to the board instead.

The board has to take it. SLUA271 states the condition plainly: “the construction of the exposed pad enables enhanced thermal and electrical characteristics. To take full advantage of this feature, the pad must be physically connected to the PCB substrate with solder. The published data for thermal performance, θ_JA, is based on a four-layer PCB incorporating vias that act as the thermal path to the layers” — the JEDEC board of JESD51-7. A datasheet θ_JA is a soldered pad with vias into planes; an unsoldered pad is a different, worse, package.

Why it must be soldered even when the heat does not matter

Many parts with an exposed pad dissipate almost nothing — a low-power regulator, an interface IC — and the temptation is to leave the pad off the paste. SLUA271 does not allow it: “not all applications require vias. The need for vias depends on the amount of power the device dissipates … The center thermal pad, however, should always be soldered to the board for mechanical strength and reliability.” The pad is most of the package’s footprint; the lead fingers around it are 0.05–0.075 mm-thick joints on lands a fraction of a millimetre wide, and a package held only by them is a package that fails in thermal cycling and drop.

There is an electrical reason too. SLOA120: “the thermal pad is usually tied to ground, and designers should ensure electrical correctness when connecting the copper planes to the thermal pad.” On many parts the die attach is conductive and the pad is the substrate connection; the datasheet says whether it must be grounded, may float, or must not be connected to anything else. Read that line before pouring.

The stencil: why the pad is printed at 50–70 %

Solder paste is printed through a stencil, and the obvious stencil — an opening the size of the pad — is wrong. SLUA271 §4.4: “designing an aperture that prints solder 1:1 with the exposed pad results in excessive metal volume that can ‘float’ the part and cause opens and other manufacturing defects.” The part rides up on the molten pool under its centre, and the fine lead-finger joints at its edge, which are thinner than the pad’s, pull open. The pad is therefore windowed: “typically, the solder-paste coverage is approximately 50 % to 70 % of the pad area”, in an array of apertures that “enables out-gassing of the solder paste during reflow and also regulates the finished solder thickness”.

Two square pads side by side. Left: a single stencil opening the full size of the pad, labelled 1 to 1, 3.1 cubic millimetres of paste, and the warning that the part floats. Right: the same pad with four square windows covering 60 percent of it, labelled 1.9 cubic millimetres, with the webs between windows marked. — Fig 3 — SLUA271's figure 4-3 in numbers, for a 5 mm pad and a 0.125 mm stencil. Printed 1:1 the pad takes 3.13 mm³ of paste, "excessive metal volume that can 'float' the part and cause opens" on lead fingers whose joints are 0.05–0.075 mm thick. Windowed to 60 % — four 1.94 mm squares — it takes 1.88 mm³, the paste can out-gas through the webs, and the solder still wets the whole pad on reflow. SLOA120 says the opposite for PowerPAD parts, whose datasheets draw their own openings.

Each window still has to release its paste. IPC-7525’s area ratio — the aperture’s open area over the area of its walls — has to be 0.66 or more for a laser-cut stencil; “experiments have shown that nickel-formed stencils print with area ratios down to 0.57”. The stencil is 0.100 to 0.150 mm thick, and “as a guide, a stencil thickness of 0,125 mm (0.005 in) for QFN and SON components is recommended”, set by the lead fingers rather than the pad: SLUA271’s example finger aperture, 0.23 × 0.8 mm in that foil, has an area ratio of 0.71, just inside the rule. A big pad’s windows are never the limiting aperture; the fingers beside it are.

One caution. SLOA120, the PowerPAD note, says of its parts: “do not use cross hatching in the stencil thermal pad opening. This significantly reduces the amount of solder paste applied and increases voiding”, and points to the stencil drawing in each datasheet. The two notes are written for different packages and different years — SLUA271’s windowed 50–70 % is for QFN and SON, revised in 2023 — and where a datasheet gives its own stencil drawing, that drawing wins.

The vias under it

The pad’s copper is one layer; the heat wants the planes. Both notes give the same array: SLUA271, “for thermally challenging applications, TI recommends that the thermal vias be placed on a pitch of approximately 1,0 mm. Per standard PCB manufacturing capabilities, 0,3 mm diameter drill holes are recommended as a starting point, but a smaller via offers less risk of solder volume loss”; SLOA120, “the recommended via diameter is 0,3 mm or less, and the recommended via spacing is 1 mm”. The vias connect to the plane solidly — “do not use a thermal relief web or spoke connection which impedes the conduction path into the inner copper layer(s)” — and how many of them actually help, and where the array stops paying, is the thermal vias article.

Their cost is the paste. Molten solder wicks down an open via, and SLOA120 names the result: “solder loss and protrusions result when excessive solder flowed through internal vias during reflow … Solder loss results in voiding and severely affects thermal conductivity.” The fixes in SLUA271’s trials, in order of cost: plugging (“vias that are plugged eliminate the risk of solder volume loss”), tenting from the top with a mask opening 0.1 mm larger than the hole (“trials have shown that via tenting from the top is less likely to produce random voids”), or on an OSP finish “not tenting any vias from the top or bottom of board has shown repeatable performance”. Tenting from the bottom traps air and “the voiding potential can increase”. SLOA120’s fallback for thin boards or big holes is vias outside the pad, at a thermal cost it says to evaluate.

What voiding costs

The joint is never perfect, and both notes set the same bar. SLUA271: “the amount of voiding post reflow in the thermal pad solder joint should not exceed 50 % in high-power applications (to be verified using an x-ray). Based on a JEDEC High K board stackup, 25 % has been determined to be a point of diminishing thermal performance returns, but TI prefers a limit of 50 % to be set.” SLOA120: “designers are encouraged to x-ray their reflowed boards to verify that at least 50 % of thermal pad area is soldered”.

Why 50 % is tolerable is in SNVA183’s simulation of solder coverage.

Plot of the percentage increase in junction-to-ambient thermal resistance against the fraction of the exposed pad that is soldered, from 100 percent down to 5 percent. The curve is flat near full coverage, 4 percent higher at half coverage, 13 percent at one fifth, 19 percent at one tenth, and climbs steeply to 34 percent at one twentieth. Vertical lines mark 75 percent soldered, the 25 percent void limit of diminishing returns, and 50 percent soldered, the maximum voiding allowed. — Fig 2 — SNVA183's figure 12(a) from the four points it quotes: with solder under the pad reduced to 50, 20, 10 and 5 %, θJA rises "by about 4 %, 13 %, 19 %, and 34 %, respectively", and "the 10 % solder coverage is a critical point". SLUA271's limits sit on the flat part: voiding "should not exceed 50 %" and "25 % has been determined to be a point of diminishing thermal performance returns" — a joint that is half soldered is only 4 % worse, and one that is barely soldered is where the curve turns up.

“When solder coverage decreases to 50 %, 20 %, 10 % and 5 %, the thermal resistance θ_JA will increase by about 4 %, 13 %, 19 %, and 34 %, respectively. The 10 % solder coverage is a critical point. Once solder coverage becomes less than 10 %, θ_JA drastically goes up.” And: “in general, the change of the thermal resistance θ_JA will be less than 5 % for the solder coverage larger than 50 %.” The curve is flat where the joint is mostly there and steep where it is mostly gone, which is what makes 50 % a sensible limit and an unsoldered pad a disaster rather than a degradation. The note adds that the critical point moves with the package — “for a 44L LLP on a 4L JEDEC board, the critical point is 20 %” — and that its un-soldered region was modelled in the middle of the pad, which real voids are not.

Voids come from the process more than the geometry. SLUA271’s trials: “an excessive soak time, which activates the majority of the flux before the melting temperature of the alloy, results in large voids”, so the profile should keep flux active through the melt; type 3 or finer paste for PowerPAD (SLOA120); no aggressive fluxes under a low-standoff part unless they can be cleaned out.

Thermal paste, thermal pads, and the other kind of thermal pad

The question “can I put thermal paste on the thermal pad” mixes two products with one name. The IC’s thermal pad is a solder joint, made with solder paste — the paste in SLUA271’s §4.1 is “a low residue, no-clean solder (SN63/Pb37 or SAC alloy) paste”, the vehicle for flux and alloy — and nothing else attaches it. Thermal grease or a gap-filler pad is an interface material for a heatsink pressed against a package top or a board; it does not solder, it does not hold the part, and on an exposed pad it leaves the joint at the 5 %-and-under end of SNVA183’s curve. Where a design needs a heatsink as well, the pad is still soldered to the board first and the heat is taken from the board’s copper or, on parts with a top-side slug, from the top.

The checklist

PCB pad equal to the package pad, with SLUA271’s 0.2 mm clearance to the lead-finger lands, non-solder-mask-defined lands around it.
Windowed stencil, 50–70 %, each window’s area ratio 0.66 or better in a 0.125 mm foil; follow the datasheet’s stencil drawing where one is given.
0.3 mm vias on a 1 mm pitch, solid to the planes, plugged or tented from the top; smaller holes if solder loss shows on x-ray.
Solder it regardless of power, for mechanical strength; check the datasheet for what the pad may be connected to.
X-ray the joint: under 25 % voids is the target, 50 % the limit; more means the profile or the via tenting, not the layout.
Solder paste, never thermal paste.

Sources

TI, SLUA271C — QFN and SON PCB Attachment, revised December 2023. §3.4 exposed-pad design and via tenting trials, §4.2–4.4 stencils, area and aspect ratios, the 50–70 % window and the 50 % / 25 % void limits.
TI, SLOA120 — PowerPAD Layout Guidelines, 2006. The package section, via size and pitch, solder loss and protrusions, the no-cross-hatch stencil rule.
TI, SNVA183B — AN-1520 A Guide to Board Layout for Best Thermal Resistance for Exposed Packages, revised 2013. Figure 12(a): θ_JA against solder coverage.