How many thermal vias, and when more stop helping

The decision rule fits in one sentence: fill the exposed pad with standard 12-mil vias on a 1 mm grid — as many as the pad physically holds, typically 9 to 16 — connect every one of them solidly to every copper plane it passes, and then stop adding vias and start adding copper area. That array turns a single via’s ~261 °C/W into 16–29 °C/W, at which point the vias are no longer the largest resistance in the path and the next degree comes from square centimetres of unbroken pour, not from hole count.

Everything below is the justification, quoted from four TI application notes and computed from the same barrel geometry their numbers come from. The companion piece is θJA is a property of the test board, not of your board: that article shows why the datasheet number cannot predict your junction temperature; this one is about the part of the board you design to fix it.

A thermal via is a copper tube, and only the tube conducts

A plated through-hole via is a thin-walled copper cylinder through the laminate. Thermally it is nothing more than a conduction path of length L (the board thickness) and cross-section A (the annulus of plating), and its resistance is the general conduction formula applied to that tube — equation 15 of TI SNVA419:

$$\theta_{VIA} = \frac{L}{\lambda_{Cu}\cdot\pi\left[r^2 - (r-t)^2\right]}$$

where r is the drill radius, t the plating thickness, and λ_Cu the thermal conductivity of copper — 4 W/cm·K in SNVA419’s units, 385 W/m·K in TI SNOA967’s.

The hole itself does nothing. SNOA967 works the air core of a standard via out to more than 400,000 °C/W — roughly five thousand times the resistance of the copper wall around it — and concludes:

The air filled drill hole of a via does not contribute much to the heat transfer rate, so almost all of the heat transfer of a standard via occurs through its sidewalls.

The same document compares that wall to the material it replaces: a solid FR4 cylinder of the same outer diameter computes to 32,595 °C/W, about 400 times worse, because copper conducts heat roughly 1,500 times better than FR4 (385 vs 0.25 W/m·K). A via is not a good thermal conductor in absolute terms; it is a spectacular one compared to the laminate it punches through, which is the only comparison the board offers.

Why one source says 261 °C/W and another says 81 °C/W

SNVA419’s headline value — the one repeated everywhere — is for a specific tube:

A typical 12 mil diameter thru hole via with 0.5 oz copper sidewalls has a thermal resistance of 261 °C / Watt.

Its stated assumptions: barrel length 0.165 cm (a 65-mil board), drill radius 6 mil (0.01524 cm), plating 0.00175 cm. SNOA967’s worked example, equation 9, arrives somewhere very different:

The sidewalls of a non-tented, non-filled via with a 0.5mm drill hole size, a sidewall copper thickness of 35µm, and a length of 1.6mm have the thermal resistance of 81 °C/W.

Both are correct, and the gap between them is the lesson. The SNOA967 via has a hole 64 % larger in diameter and walls twice as thick, which is about 3.2 times the copper cross-section — and almost exactly 3.2 times less thermal resistance. SNOA967 adds the caveat that matters for anyone copying numbers:

Note that the sidewall thickness of a via is often different from the copper plating thickness and depends on via dimensions and the manufacturing process of the PCB manufacturer.

So “what is a thermal via worth” has no single answer, only a formula with your geometry in it. SNVA419 itself prices out the variations: the same 12-mil via with 1 oz plating drops to 140 °C/W for a 10–20 % board cost adder, and an 8-mil via plated fully closed reaches 128 °C/W. The via calculator evaluates the barrel formula for your actual hole, plating and board thickness rather than anyone’s “typical” one.

Vias in parallel, and where 1/N stops being true

Vias under a pad share the same two isothermal surfaces — top copper above, plane below — so they combine like parallel resistors, and the arithmetic really is that simple. SNVA419’s rule and worked example:

Place as many thermal vias as will fit underneath the exposed pad to form an array, with 1mm spacing. Connect the vias to as many layers of copper as possible to spread the heat away from the package and to the PCB surface where it can transfer to the ambient air.

For a 14-pin eMSOP with a 3.1 × 3.2 mm pad, that is a 4 × 4 array of 16 vias: 261 / 16 = 16.3 °C/W. A TO-PMOD-7’s larger 5.35 × 8.54 mm pad takes at least 40, for 6.5 °C/W. But TI SNVA951 states the limit in the same breath as the rule:

The thermal resistance of each via is in parallel with its neighbor, so the overall resistance will decrease with an increasing number of vias; up to some limiting point.

The array itself follows 1/N indefinitely; the junction temperature does not, because the array is one term of a series chain. Once 261/N has fallen below the package’s θ_JC and the board’s spreading-plus-convection resistance, dividing it further is polishing the smallest number in a sum.

The bottleneck moves: what the array cannot fix

Lay the terms side by side and the story tells itself. With SNVA419’s eMSOP (θ_JC = 7.3 °C/W) on 15 cm² of unbroken 1-oz copper (about 33 °C/W by SNVA951’s guideline, next section), one via makes the barrel 87 % of the total. Sixteen vias make it 29 %. Forty make it 14 % — and going from 16 to 40 vias saves less than 10 °C/W while the other 40 °C/W sit untouched.

This is the same series-chain argument as the θJA article, pointed at the one term the via array controls: after the first full grid under the pad, the bottleneck has already moved on, and the design effort should move with it — to copper area, copper weight, and an unbroken path to the board surface.

Under the pad first: distance costs 71 °C/W per centimetre

Where the vias go matters as much as how many. SNVA951:

the most effective place for the thermal vias is under the DAP. However, placing vias around and near the regulator will also help to reduce the thermal resistance of the board.

The reason falls out of SNVA419’s resistor lattice. A via directly under the pad receives heat straight from the exposed pad. A via a centimetre away receives it only after it has crossed that centimetre of top copper laterally — and SNVA419’s Table 1 puts one 1 cm square of 1-oz copper at 71.4 °C/W. That square goes in series with the remote barrel:

So a via 1 cm out presents roughly 71.4 + 261 ≈ 332 °C/W to the junction, and one 2 cm out about 404 °C/W — still worth having, since it lands in parallel with everything else, but worth a third less than the same drill hit under the pad. Fill the pad before you scatter the ring.

The PowerPAD pattern: 0.3 mm holes on a 1 mm grid

For exposed-pad packages, TI SLOA120 turns all of this into a manufacturable prescription. The pad on the board is solder-mask defined — an opening in the mask sized to the package’s thermal pad — and the vias sit inside it:

The recommended via diameter is 0,3 mm or less, and the recommended via spacing is 1 mm.

Two details in SLOA120 are easy to miss and both are thermal, not cosmetic. First, the vias must connect to the internal plane around their whole circumference:

Do not use a thermal relief web or spoke connection which impedes the conduction path into the inner copper layer(s).

A thermal relief is a deliberately added thermal resistance — that is what makes it solderable — placed at exactly the point where this via exists to conduct. Second, leave the vias out of the mask, with a 0.05 mm exposed copper ring around each at the bottom plane; SLOA120 is blunt that covering them “causes excessive voiding”. The same barrel, incidentally, is doing electrical work too — a ground stitch under the pad is the shortest return path the package has, the argument of the via is the decoupling.

Open, plugged or external: what solder does during reflow

An open via in the middle of a solderable pad is a drain. During reflow, solder can wick down the barrel instead of staying in the joint — SLOA120 calls the failure modes solder loss (voids under the pad, which are thermal insulation exactly where the heat enters) and protrusions (solder bumps on the far side of the board). Its acceptance test is explicit: X-ray the reflowed board and confirm at least 50 % of the thermal pad area is soldered. The exposed pad stencil calculator sizes the stencil windows that print the pad and the via array under it, and prices the voiding in θJA.

On plugging the vias shut, SLOA120 is carefully lukewarm:

Vias may be plugged to prevent solder loss and protrusions. This often produces the best thermal performances but is not necessary or recommended because of the increased cost of PCB boards and because solder tends to wet the upper surface first before filling the vias.

SNVA419 puts numbers on that cost judgement: plating vias fully closed “can double or triple the cost of your PCB design”, against a thermal gain from 16.3 to 8 °C/W for the 16-via array — while simply specifying 1 oz plating on standard open vias gets 8.75 °C/W for a 10–20 % adder. SNOA967 frames filling as the escalation step, not the default:

Filled vias should be considered if even multiple parallel standard vias do not provide a sufficiently fast heat transfer rate to meet system specifications.

The third option, from SLOA120, is external-only vias — outside the pad, where they cannot wick — for thin boards or holes over 0.3 mm. That trades the wicking problem for the 71-°C/W-per-square lateral detour of the previous section, and SLOA120 warns it “might reduce thermal performance significantly”.

Copper area is the other half of the budget

Once the pad is full of vias, the remaining resistance belongs to the copper. SNVA951, introducing the θJA-versus-copper-area curves that modern regulator datasheets carry:

The important point brought out by these curves is that more area translates into smaller thermal resistance and better thermal performance. Also, it is evident that a point-of-diminishing-return is reached at large values of copper area.

Its section 7.1 compresses those curves into one guideline for a package with an exposed pad — an unbroken 1-oz plane, top and bottom well connected (that is what the via array is for), 1 W dissipated:

$$\theta_{JA} \approx \theta_{JC} + \frac{500}{A_{Cu}\,[\mathrm{cm^2}]}$$

TI bound the estimate at about ±50 %, but its shape is the design guidance: the first 20 cm² are worth tens of °C/W, the next 20 are worth 12.5, the 20 after that 4.2. It also agrees with SNVA419’s independent rule of thumb — 15.29 cm² of two-sided board per watt for a 40 °C rise — to within a few °C/W, which is the kind of cross-check two documents should survive.

Copper weight scales the lateral term directly. SNVA419: at least 1 oz for any DC-DC design, 2 oz above 3 W, 4 oz above 6 W — and its measured pair of otherwise identical 3 × 3-inch boards went from 28.3 to 21.2 °C/W, a 25 % improvement, on the copper weight change alone. (SNVA951, written a decade later for automotive parts, tightens the middle threshold to 2 oz at 2 W.) The cross-section arithmetic is the same one behind the trace-width calculator: thickness times width is the conduction area, for amps and for watts alike.

Do not cut the top layer

The top copper deserves its own warning because it does two jobs at once: it is where the heat enters the board, and — SNVA951 —

Most of the heat will be dissipated to ambient through the layer that is on the same side as the converter.

Heat spreads radially from the package, and a routed trace across that flow is a dam. SNVA419 measured it on three otherwise identical boards: a wide cut in the top copper perpendicular to the heat flow raised the source temperature 5.5 °C; the same cut parallel to the flow — radial, along the “pizza slice” in SNVA951’s phrase — cost only 1.5 °C.

If two supposedly identical boards run at different temperatures, look for the signal trace someone routed across the pour under the regulator before suspecting anything else.

A worked example, end to end

SNVA951’s section 9 runs the whole chain for an LMR33630 buck converter (HSOIC, exposed pad) and then measures the result, which makes it the honest test of everything above. The conditions: 24 V in, 3.3 V out at 3 A, 85 °C ambient, T_J ≤ 125 °C.

The arithmetic, straight from the document:

efficiency        ≈ 87 % at 25 °C  → call it 85 % at 85 °C
dissipation       P_D ≈ 1.7 W − 0.13 W (inductor)  ≈ 1.57 W
budget            θ_JA ≤ (125 − 85) / 1.57 ≈ 25 °C/W  → design to 24
copper area       500 / (24 − 4.3) ≈ 25 cm²   (TI's spreadsheet: ≈ 30 cm²)
via array         12-mil, 0.5-oz vias, 1 mm grid under the pad
measured          at 25 °C ambient: case top 56 °C → T_J ≈ 63 °C
                  θ_JA ≈ (63 − 25) / 1.57 ≈ 24 °C/W

The measured board lands on the calculated number — with one detail SNVA951 states and that is easy to skip: the EVM was measured at 25 °C ambient, not the 85 °C of the design, so the comparison is on θ_JA rather than on junction temperature. Put the design ambient back in and the same 24 °C/W gives 85 + 1.57 × 24 ≈ 123 °C, inside the 125 °C limit. One more figure from the same section is worth carrying around: the copper that actually participates is only about 18 times the footprint of the heat-generating components — TI’s “thermal footprint” — so a 59 cm² EVM behaves like the ~29 cm² around its converter and inductor, and crowding two hot parts closer than about twice their package dimension makes their footprints overlap and both run hotter.

The checklist

• Via count: as many as fit under the exposed pad on a 1 mm grid; a 3 × 3 mm pad takes 9, a 3.1 × 3.2 mm pad 16. More than ~20 buys tenths.
• Via size: 12 mil / 0.3 mm or smaller in the pad — bigger holes wick. Standard 0.5-oz plating is 261 °C/W each; 1-oz plating is the cheap upgrade, plugging the expensive one.
• Connection: solid to every plane, full circumference, no thermal reliefs, no mask over the vias.
• Placement: pad first, then near the package; every centimetre of distance adds ~71 °C/W of 1-oz copper in series.
• Copper: unbroken pour on the component side, ~15 cm² per watt as the opening bid, 2 oz once dissipation passes 2–3 W.
• Routing: nothing cut across the radial heat flow on the spreading layers.
• Verification: X-ray for ≥50 % pad solder coverage; thermal camera plus Ψ_JT for the junction estimate on the finished board.

Sources

• TI SNVA419 — AN-2020 Thermal Design By Insight, Not Hindsight — the via formula and the 261/140/128 °C/W geometries, the 1 mm array rule and both array examples, the 71.4 °C/W copper square, the copper-weight thresholds, and the measured cost of cutting the thermal path.
• TI SNOA967 — Temperature sensors: PCB guidelines for surface mount devices — the 81 °C/W worked via, the air-core and FR4-cylinder comparisons, the material conductivities, and the filled-via escalation rule.
• TI SLOA120 — PowerPAD Layout Guidelines — the 0.3 mm / 1 mm pattern, solid via connections, mask rules, solder loss and protrusions, plugging, external-only vias, and the 50 % X-ray acceptance test.
• TI SNVA951 — PCB Thermal Design Tips for Automotive DC/DC Converters — the parallel-vias limiting point, the copper-area guideline θJA ≈ θJC + 500/A, the thermal footprint, and the measured LMR33630 design example.

Updates

• 2026-09-13 — Fig 10’s via-array box no longer quotes 16 vias and 16.3 °C/W for the LMR33630 HSOIC: that count is SNVA419’s eMSOP example, and neither document gives a via count for the HSOIC pad. The box now states the rules the example follows.
• 2026-09-13 — The worked example now states that SNVA951’s measurement was made at 25 °C ambient, so θ_JA = (63 − 25)/1.57 ≈ 24 °C/W; read against the 85 °C design ambient the arithmetic did not close.
• 2026-09-13 — Fig 5’s description corrected: a via 2 cm from the pad is worth about two thirds of one under it (261 against 404 °C/W), not 40 percent.