θJA is a property of the test board, not of your board

Every regulator datasheet quotes a junction-to-ambient thermal resistance, in °C/W, and it is the most-misused number in the document. People multiply it by their power dissipation, add ambient, get a junction temperature that looks fine, and ship a board that runs 30 °C hotter than the calculation said.

The number is not wrong. It is an answer to a question about a different board.

What θJA actually is

Junction to ambient is not a property of a package. It is a whole chain of resistances in series, and the package is only the first link:

Written out:

$$T_J = T_A + P \cdot \theta_{JA} \qquad \theta_{JA} = \theta_{JC} + \frac{\theta_{VIA}}{n} + \theta_{Cu} + \theta_{SA}$$

That chain is the shortest path through SNVA419’s Figure 3, which is really a mesh: the laminate between the copper layers appears in it as its own vertical term, θ_FR4, and heat spreads through several of these paths at once. The four-term sum is the simplification worth carrying in your head, not the whole network.

Only θ_JC — junction to case — belongs to the part you bought. Everything to the right of it is copper you drew. TI put it plainly in SNVA419:

The amount of variability in PCB designs is significant. You can see that the thermal resistance depends on board size, airflow, PCB thickness and many other parameters.

Which is exactly why the standards exist. JESD51-1 through JESD51-11 specify a test board — its size, its copper, its layout — so that two parts measured the same way can be compared. That is what a datasheet θJA is for: comparing parts against each other, not predicting your junction temperature.

TI’s own instruction follows: always check the data sheet to see what PCB parameters were used to measure θJA, and the final design, and thus θJA, depends on the end user.

The number that actually constrains you

Before the layout rules, the one figure worth memorising, because it sizes the problem before you have drawn anything:

With only natural convection (i.e. no airflow), and no heat sink, a typical two sided PCB with solid copper fills on both sides, needs at least 15.29 cm² (≊ 2.37 in²) of area to dissipate 1 watt of power for a 40°C rise in temperature.

That is roughly a 4 cm × 4 cm square of board, entirely given over to spreading heat, per watt. If your design dissipates 3 W and the whole board is 5 cm × 5 cm, no arrangement of vias will save it — you need airflow, a heat sink, or a more efficient converter. Knowing that on day one is worth more than any amount of careful via placement on day thirty.

The terms you control

Vias. A typical 12 mil through-hole via with 0.5 oz copper sidewalls is 261 °C/W. On its own that is enormous — but they are in parallel, so n of them is 261/n. TI’s rule: place as many as will fit under the exposed pad, on a 1 mm grid, and connect them to as many copper layers as possible. Ten vias turns 261 °C/W into 26 °C/W, which is the single cheapest improvement available. The via calculator gives the thermal resistance for your actual hole and plating rather than the typical one.

Copper thickness. Lateral spreading resistance is inversely proportional to copper thickness, so the weight matters directly. TI’s thresholds: at least 1 oz for any DC-DC design, 2 oz above 3 W, 4 oz above 6 W. For reference, one 1 cm square of 1 oz copper is about 71.4 °C/W laterally.

Breaks in the path. This is the one that produces surprises, because it is invisible on a schematic. Heat spreads radially from the source, and a trace cut through the plane perpendicular to that flow is a wall:

Traces perpendicular to the heat flow will create high impedances (speed bumps) for the heat and create hot spots (traffic jams). If traces through the copper heat spreader are unavoidable try to make them run parallel to the heat transfer, which flows radially from the heat source.

A single signal trace routed across the ground pour under a regulator can measurably raise its junction temperature. If you have ever had two “identical” boards run at different temperatures, this is the first thing to look for.

Heat-sink placement, which TI rate as mattering as much as heat-sink selection — a heat sink over a thermally isolated part of the board does very little.

Multiple sources. Superposition almost works: solve for one source at a time with the others open, and sum the temperature rises. TI’s caveat is only that some of the resistances have non-linear dependencies on temperature, so there will be some error in the result — the note does not say in which direction. Treat it as a good estimate, not a bound.

So what should you do with the datasheet number?

Use θJA to shortlist parts, never to predict a temperature. Two regulators measured to the same JESD51 board can be compared honestly. Neither tells you what your board will do.

Use ΨJT to measure, not to calculate. Most modern datasheets also give a junction-to-top characterisation parameter. Unlike θJC it is defined for the real mounted case, so you can put a thermocouple or an IR camera on the package top, measure the case temperature under load, and get a junction estimate on your board:

$$T_J \approx T_{top} + \Psi_{JT} \cdot P$$

That is the honest number, and it takes ten minutes with a thermal camera.

Design the copper first, then check the number. Board area per watt, via array under the pad, copper weight, no cuts through the spreader. Get those right and θJA becomes a detail; get them wrong and no amount of arithmetic on the datasheet value will rescue the design. The LDO thermal calculator runs that direction — dissipation and ambient in, the θJA and the copper area you need out — which is the form the question actually takes at layout time.

Sources

• TI SNVA419 — AN-2020 Thermal Design by Insight, Not Hindsight — the resistance network, the JESD51 caveat, the 15.29 cm²/W rule, the 261 °C/W via, the copper-weight thresholds and the superposition method.
• TI SNOA967 — PCB Layout Guidelines for Temperature Sensors — the same physics from the other direction: how to stop board heat reaching a part.
• TI SLOA120 — PowerPAD Layout Guidelines — exposed-pad soldering and via arrays in detail.
• TI SLUAAD6 — Thermal performance in high power density designs — where natural convection stops being enough.

Updates

• 2026-09-13 — The superposition caveat now matches SNVA419: the note says only that the temperature-dependent resistances introduce some error, not that the method under-predicts.
• 2026-09-13 — The 15.29 cm²-per-watt quotation restored to the source’s wording, and a note added that the four-term chain is the shortest path through SNVA419’s mesh model, which also carries a laminate term.