Where to put a bypass capacitor: mounting, distance, BGAs

The vias and traces a bypass capacitor connects through add as much inductance as the part, 0.4 to 4 nH for one 0402 per XAPP623, and set where it resonates.

“As close to the pin as possible” is the whole of most placement advice and it hides the two things that actually decide whether a bypass capacitor works. The first is what the capacitor is connected through. Xilinx’s XAPP623 puts a number on it: the lands, traces and vias of a capacitor mounting “contribute anywhere from 300 pH to 4 nH of inductance depending on the specific geometry”, and that mounting “typically contributes about the same amount or more inductance than the capacitor’s own parasitic inductance”. A 0402 that is 0.4 nH on one land pattern is 4 nH on another, and the part resonates where the board says. The second is distance, and it is a phase limit rather than an inductance one: the disturbance has to reach the capacitor and the relief has to come back, at “approximately 166 ps per inch” in FR-4, well inside a quarter wave at the frequency the capacitor is there for.

Those two rules give different answers for different capacitors. A 1 nF has to sit within about 30 mm of its pins; a 4.7 µF “can be placed anywhere on the board”. For the 100 nF that most pins get, the distance is loose and the mounting is everything. The bypass placement calculator does the sums for any part, land pattern, via and distance; this article is what the notes say and why.

What the capacitor is connected through

XAPP623 draws the current loop of a mounted capacitor — “through one power plane, up through one via, through the connecting trace to the land, through the capacitor, through the other land and connecting trace, down through the other via, and into the other plane” — and since “the inductance of a current path is proportional to the area of the loop the current traverses”, everything about placement is about shrinking it. Its figure 6 is the clearest statement of what that is worth: the same 0402 on four land patterns.

Four 0402 capacitor land patterns side by side, each two rectangular pads with a capacitor body between them. A: long traces run from each pad end to a via, labelled 4 nanohenries, bad. B: the vias sit hard against the pad ends, 0.8 nanohenries. C: the vias sit beside the pads, 0.6 nanohenries. D: two vias beside each pad, 0.4 nanohenries. — Fig 1 — XAPP623's figure 6, redrawn: the same 0402 capacitor on four land patterns, with the mounting inductance the note gives each. 4 nH with traces to the vias, 0.8 nH with the vias butted against the lands, 0.6 nH beside them, 0.4 nH with two per side — a factor of ten from routing alone, on a part whose own inductance is under 1 nH.

The rules that follow are the note’s own. “Wherever possible, there should be no connecting trace — the via should butt up against the land itself. Additionally, the connecting trace should be made as wide as possible.” Vias beside the lands beat vias at their ends; two vias per land beat one; via-in-pad, where the fab allows it, “is another good option”. And one prohibition without hedging: sharing vias between capacitors “should not be used under any circumstances”, because “if a second capacitor is connected into the vias of an existing capacitor, it only improves the PDS by a very small amount. It is better to reduce the total number of capacitors and maintain a one-to-one ratio of lands to vias.”

TI’s SLOA069 gives the numbers for anything longer than a land. “Common PCB traces have self-inductances that measure between 6 nH and 12 nH per centimeter”, so “even a couple of millimeters … adds 1.2 nH”, and its conclusion is blunt: “using PCB traces to make connections to decoupling capacitors simply cannot work!” The via has its own formula there, $L \approx 5.08\,h\,[\ln(4h/d) + 1]$ nH with the height and diameter in inches, and its own examples: “a 0.4-mm diameter via through a 1.5-mm thick PCB has an inductance of 1.1 nH”, while a 0.15 mm microvia to an adjacent layer is 0.072 nH. “Height is the predominant factor, so blind vias are much more important than microvias.” XAPP623 says the same from the other side: “vias traverse a full board stackup on their way to the device when capacitors are mounted on the underside of the board”, and “because there are two of these paths in series with each capacitor, twice this value should be added”.

What the mounting does to the capacitor

The reason the inductance matters is that it sets the frequency at which the capacitor is any use. XAPP623 separates “the capacitor’s self-resonant frequency” — the datasheet number — from “the effective resonant frequency of the mounted capacitor when it is part of the system”, which “is considerably” lower, and works one: a 10 nF X7R with 0.9 nH of its own, 53 MHz on the datasheet, gets 0.8 nH of mounting and resonates at 38 MHz.

$L_{IS} = L_{SELF} + L_{MOUNT}, \qquad F_{RIS} = \frac{1}{2\pi\sqrt{L_{IS}\,C}}$

SLOA069’s example is the same arithmetic at the other end of the spectrum, and it is the one to remember.

Plot of mounted resonant frequency against trace length from zero to 15 millimetres, log frequency axis. The upper curve, for a 27.77 picofarad capacitor with 0.23 nanohenries, starts near 2 gigahertz and falls to 314 megahertz at 15 millimetres. The lower curve, for 100 nanofarads with 0.9 nanohenries, starts at 16.8 megahertz and falls to about 5 megahertz. — Fig 3 — What trace does to the resonance, at SLOA069's 6 nH/cm. Its own example, a 27.77 pF part with 0.23 nH meant for 1.9 GHz: 1.5 cm of trace adds 9 nH and "the series self-resonance becomes 314 MHz. This PCB layout is entirely unsuitable." The same 9 nH takes a 100 nF from 16.8 MHz to 5.06 MHz; the ratio is the same factor of 3.3, because the board's inductance swamps the part's in both cases. "Even a couple of millimeters … adds 1.2 nH."

The capacitor that was chosen for 1.9 GHz is, after 1.5 cm of trace, a 314 MHz capacitor. Nothing about the part changed. The same 9 nH does the same to a 100 nF in proportion — a factor of three, not of six, only because the 100 nF started with more of its own — and it is why the mounted resonance, not the datasheet’s, is the number to design a decoupling network around. “Since a decoupling capacitor is only effective at a narrow band of frequencies around its resonant frequency, it is important that the resonant frequency be taken into account.”

How far is too far

TI’s SCBA007 measured it the direct way: an ABT541 with all eight outputs switching at 33 MHz, and the bypass capacitor “at different distances from the power pin (0.3, 1, and 2 inches)”. The ringing on V_CC “increases as the capacitor is moved away from the power pin”, and with the capacitor at the pin rather than 0.3 inch away “there is dramatic improvement”. Its explanation is the loop again — the inductance “is directly proportional to the distance between the lines as well as the length of the lines” — and its rule is the familiar one: “it is always important to minimize the loop between the V_CC pin, the ground, and the bypass capacitor.”

XAPP623 gives the rule a limit rather than a direction. Between the pins and the capacitor, the plane pair is a transmission line: “there is a finite time delay between the start of the disturbance at the FPGA power pins and the start of the capacitor’s view of the disturbance … There is another delay of the same duration for the compensation current from the capacitor to reach the FPGA.” Past a quarter wavelength “the energy transferred to the FPGA is negligible”, and it climbs to full effect at zero distance. The target the note sets: “one tenth of a quarter wavelength is a good target. This leads to placing a capacitor within one fortieth of a wavelength of the power pins it is decoupling. The wavelength corresponds to F_RIS, the capacitor’s mounted resonant frequency.”

$\lambda = \frac{1 / F_{RIS}}{166\ \text{ps/inch}}, \qquad R_{PLACE} = \frac{\lambda}{40}$

Log-log plot of placement radius against capacitance from 100 picofarads to 10 microfarads, for 1.6 nanohenries in the system. The line rises as the square root of capacitance: about 10 millimetres at 100 picofarads, 30 millimetres at 1 nanofarad, 0.3 metres at 100 nanofarads, 2 metres at 4.7 microfarads. A horizontal band marks 50 to 150 millimetres, the size of a typical board. — Fig 2 — XAPP623's placement radius, λ/40 at the mounted resonance, against capacitance for its 1.6 nH example at 166 ps/inch. The note's two cases are marked: 1 nF within 30.4 mm ("1.2 inches"), 4.7 µF within 2.08 m ("can be placed anywhere on the board"). The shaded band is the size of most boards: everything above about 10 nF clears it, and only the small, high-frequency parts are placement-critical.

The note’s example is a 1 nF in 0402 with 1.6 nH in the system: 125.8 MHz, a 7.95 ns period, a 47.9 inch wavelength, and “the target placement radius for capacitors of this size is within 1.2 inches (3.0 cm) of the power and ground pins they are decoupling”. Then the consequence that most placement advice misses: “a radius of 1.2 inches is not terribly difficult to achieve … It does not require placing capacitors directly underneath the device on the opposite side of the PCB.” And for the big parts, “the target placement radius expands quickly as the resonant frequency goes down. A 4.7 µF capacitor, for example, can be placed anywhere on the board, as its target radius of 98 inches is much bigger than most PCBs.” Placement is by value: the smallest capacitors nearest, “moving farther away from the FPGA with increasing size”.

Under the BGA, or around it

The two notes that address BGAs agree on the physics and differ on the board, and the difference is instructive. XAPP623’s position: “it is not necessary to place high-frequency capacitors within the footprint of the FPGA. It is perfectly acceptable to place all capacitors around the periphery of the device, provided all V_CC planes have a Ground plane adjacent to them, separated by a dielectric less than 4 mils in thickness.” Where the plane pair is in the top half of the stack, “it is advantageous to place capacitors on the top surface of the board, around the periphery of the device” — short vias beat a shorter distance.

TI’s SPRABV2 is written for finer pitches, where “placing caps in between ball vias is usually impossible”, and its answer is to get them underneath anyway: “skip every other row and share every via with two power or ground balls. This will allow caps to fit directly underneath the part.” This is not the via sharing XAPP623 forbids — that was two capacitors on one via; this is two balls on one via, with each capacitor still on its own — and TI limits it: “sharing more than two power/gnd balls to one via is discouraged because of the extra inductance”. The rest of its recipe: “one 0.1 µF cap (in the smallest possible package size, to reduce lead inductance)” for every two power balls, “one 15 µF or larger bulk cap for every 10 or so power balls, placed as closely as practical to the chip”, and a priority that matches XAPP623 exactly: “Be absolutely sure that the traces for decoupling caps are as short as humanly possible. Where you place them in relation to the BGA is a secondary concern to this because planes have very low inductance. Shortening the cap traces to/from the ground/power plane is THE MOST IMPORTANT concern for making a low inductance connection.”

Above a few hundred megahertz neither placement helps. SPRABV2: “above approximately 250 MHz, PCB mounted capacitors are not very effective”; what works is inter-plane capacitance, a power and ground pair “separated by an extremely thin (<10 mils) layer of dielectric”, whose “only lead … is the tiny length from the chip’s die to the plane and back”, effective “to 10+ GHz”. XAPP623 calls the same structure a sandwich and wants V_CC planes “directly adjacent to GND planes in the stackup”. ADI’s MT-101 closes the loop at the low end with the rule every note shares: the high-frequency capacitor “must be as close to the chip as possible”, connected to “a low impedance ground plane” through “short traces or vias”, because otherwise “the inductance of the connecting trace will have a negative impact on the effectiveness of the decoupling”.

The checklist

Via against the land, or in it. No trace between them; if one is unavoidable, as wide as it is short. XAPP623’s 4 nH pattern and SLOA069’s “couple of millimeters” are the same mistake.
One pair of vias per capacitor. Never two capacitors on one via. Two balls on one via under a BGA is a different thing and is allowed, in moderation.
Small parts close, big parts anywhere. The radius scales with √C: centimetres for nanofarads, metres for microfarads. Spend the placement effort on the 1–10 nF parts.
Shortest vias, not shortest distance. A part on the side whose plane pair is nearest beats a part under the chip through the whole stack. Blind vias to an adjacent plane are worth more than microvias.
Design to the mounted resonance. Add the mounting to the part’s inductance before deciding what frequency it covers.
Planes for everything above 250 MHz. Thin dielectric between power and ground is the only decoupling with no lead.

Sources

Xilinx, XAPP623 — Power Distribution System Design: Using Bypass/Decoupling Capacitors, v2.1, 2005. Mounting inductance and figure 6, L_IS and the mounted resonance, the placement section with its 166 ps/inch, λ/40, 1 nF and 4.7 µF examples, the layout example and the stackup advice.
TI, SLOA069 — How (Not) to Decouple High-Speed Operational Amplifiers. Trace inductance 6–12 nH/cm, the 1.9 GHz to 314 MHz example, the via formula and its 1.1 nH and 0.072 nH cases.
TI, SCBA007 — The Bypass Capacitor in High-Speed Environments. The ABT541 measurements at 0.3, 1 and 2 inches.
TI, SPRABV2 — BGA decoupling and PDN design. Capacitors under the BGA by via sharing, the per-ball counts, the 250 MHz limit and inter-plane capacitance.
ADI, MT-101 — Decoupling Techniques. The localized high-frequency decoupling recommendation.