100nF

ADC noise floor calculator

An ideal N-bit converter's SNR is 6.02N + 1.76 dB over dc to fs/2: 74 dB for 12 bits. The noise floor on an FFT plot sits a further 10 log10(M/2) below that, because each bin is only fs/M wide — 107 dB for a 4096-point FFT. That floor is not the SNR, and confusing the two is the mistake this page exists to prevent. Enter the resolution, the sample rate and, if you have them, the measured SNR and THD; get the noise in volts and nV/√Hz, the in-band SNR after process gain, the FFT floor, SINAD, ENOB, and the SNR ceiling your clock jitter imposes.

0 dB-20 dB-40 dB-60 dB-80 dB-100 dBfull-scale sinerms noise, SNR 74.0 dBFFT floor, +33 dB
Fig 1 — 12 bits: ideal SNR 74.0 dB below full scale, FFT floor 107 dB below.
Ideal SNR, 12 bits, dc to fs/2
74.0 dB
1 LSB · quantization noise, rms
488 µV · 141 µV
Noise implied by 74.0 dB · density
141 µV rms · 22.3 nV/√Hz
FFT noise floor, 4096 points
107 dB below full scale (SNR + 33 dB)
ENOB
12.00 bits

How this is calculated

Standard: ADI MT-001 (Kester) Eq 4, 9, 10; MT-003 Eq 1, 2, 12; MT-031 Eq 4

erms=q12,q=VFS2Ne_{rms} = \frac{q}{\sqrt{12}}, \quad q = \frac{V_{FS}}{2^N}
rms quantization noise, from a sawtooth error of peak-to-peak amplitude one LSB. MT-001 Eq 4.
SNR=6.02 N+1.76 dB,over dc to fs/2\text{SNR} = 6.02\,N + 1.76\ \text{dB}, \quad \text{over dc to } f_s/2
Full-scale sine against the quantization noise. The 1.76 dB is 20 log10 of √(3/2) and does not depend on N. MT-001 Eq 9.
SNRBW=6.02 N+1.76+10log⁡10 ⁣(fs2 BW)\text{SNR}_{BW} = 6.02\,N + 1.76 + 10\log_{10}\!\left(\frac{f_s}{2\,BW}\right)
Process gain: the noise outside the signal bandwidth is filtered away. MT-001 Eq 10.
FFT floor=SNR+10log⁡10 ⁣(M2)\text{FFT floor} = \text{SNR} + 10\log_{10}\!\left(\frac{M}{2}\right)
The FFT is a spectrum analyser of bandwidth fs/M. This is the average floor of the plot, not the converter's SNR. MT-001 p. 6, MT-003 p. 1.
SINAD=−10log⁡10 ⁣(10−SNR/10+10−THD/10)\text{SINAD} = -10\log_{10}\!\left(10^{-\text{SNR}/10} + 10^{-\text{THD}/10}\right)
Noise and harmonic distortion combine root-sum-square. MT-003 Eq 12.
ENOB=SINAD−1.76+20log⁡10 ⁣(AFSAin)6.02\text{ENOB} = \frac{\text{SINAD} - 1.76 + 20\log_{10}\!\left(\frac{A_{FS}}{A_{in}}\right)}{6.02}
The SNR formula solved for N with SINAD in place of SNR, corrected to full scale for a smaller test signal. MT-003 Eq 1 and 2.
SNRjitter=20log⁡10 ⁣(12πfin tj)\text{SNR}_{jitter} = 20\log_{10}\!\left(\frac{1}{2\pi f_{in}\, t_j}\right)
The SNR of a perfect converter whose only noise is sampling-clock jitter. MT-031 Eq 4.
en=ermsfs/2e_n = \frac{e_{rms}}{\sqrt{f_s / 2}}
Noise spectral density, derived: MT-001 states the quantization noise is spread uniformly over dc to fs/2, so its density is the rms over the square root of that bandwidth.

Assumptions

What sets an ADC's noise floor

An ideal converter's only noise is quantization: the ±½ LSB it is allowed to be wrong by. MT-001 models that error as a sawtooth of peak-to-peak amplitude q, one LSB, and its rms value is q/√12. Against a full-scale sine whose rms is 2Nq / 2√2, the ratio comes out as 6.02N + 1.76 dB — and MT-001's insistence is that the figure is definedover dc to fs/2. That bandwidth is what the two corrections below act on.

The first is process gain. The quantization noise is spread across the whole Nyquist band; if the signal occupies less and a digital filter removes the rest, the in-band SNR rises by 10 log10(fs/ 2BW). The second is the FFT floor, which is the one that confuses people: an FFT is a spectrum analyser with a bandwidth of fs/M, so its average floor sits 10 log10(M/2)below the converter's noise. The floor on a plot is not the SNR. Averaging FFTs does not lower it; a longer FFT does.

Real converters add distortion, and MT-003 defines how the pieces combine: SINAD is noise and harmonics together, root-sum-square, and ENOB is the SNR formula solved for N with SINAD substituted. A jittery clock adds a third floor of its own, MT-031's 20 log10(1 / 2πf tj), which depends on the input frequency and not at all on the resolution.

Worked example: an ideal 12-bit ADC and a 4096-point FFT

The defaults are MT-001 Figure 6: 12 bits at 80 MSPS with a 2 V span, analysed with a 4096-point FFT.

1 LSB          q = 2 V / 2¹²                          = 488 µV
rms quantization noise   q / √12                     = 141 µV
full-scale rms           2 V / 2√2                    = 707 mV
SNR            20 log(707 mV / 141 µV)               = 74.0 dB   (6.02 × 12 + 1.76)

FFT process gain         10 log(4096 / 2)             = 33.1 dB
FFT noise floor          74.0 + 33.1                  = 107 dB below full scale

noise density            141 µV / √(40 MHz)           = 22.3 nV/√Hz

The calculator reports 74.0 dB, 33 dB and 107 dB, which are MT-001's numbers. MT-003 repeats the exercise with M = 8192 and gets 36 dB and 110 dB; enter 8192 and so does the tool. For a real part, MT-003's AD9444 at 80 MSPS measures SNR 73.42 dB and THD 86.31 dB: enter both and SINAD comes out at 73.20 dB and ENOB at 11.87 bits, against a 14-bit label — the document's own tabulated values.

Where the noise floor model stops being valid

Common ADC noise mistakes

Further reading