ADC noise floor calculation: SNR, process gain and the FFT

The noise floor of an ideal N-bit converter is its quantization noise, and the signal-to-noise ratio that follows is

$\text{SNR} = 6.02\,N + 1.76\ \text{dB}, \quad \text{over dc to } f_s/2$

— 74.0 dB for 12 bits, 86.0 dB for 14, 98.1 dB for 16. But the floor on an FFT plot of that same 12-bit converter sits at 107 dB below full scale, not 74, because the FFT is a spectrum analyser with a bin width of f_s/M and pushes the noise down by 10 log₁₀(M/2). Both numbers are correct. They answer different questions, and confusing them is the mistake this article exists to prevent. Every figure here comes from Walt Kester’s tutorials at Analog Devices — MT-001 for the derivation and the FFT floor, MT-003 for SINAD and ENOB, and MT-031 for the limit the clock imposes — and the ADC noise floor calculator runs the whole chain for any resolution and sample rate.

Where 6.02N + 1.76 dB comes from

An ideal converter is allowed to be wrong by ±½ LSB. MT-001 models the error on any signal that spans more than a few LSBs as a sawtooth of peak-to-peak amplitude q, one LSB, uncorrelated with the signal. The mean-square value of a sawtooth of amplitude ±q/2 integrates to q²/12, so the rms quantization noise is

$e_{rms} = \frac{q}{\sqrt{12}}$

A full-scale sine has a peak amplitude of 2^Nq/2 and an rms of 2^Nq / 2√2. The ratio of the two, in decibels:

$\text{SNR} = 20\log_{10}\!\left(\frac{2^N q / 2\sqrt{2}}{q/\sqrt{12}}\right) = 20\log_{10}\!\left(2^N\right) + 20\log_{10}\!\left(\sqrt{\tfrac{3}{2}}\right) = 6.02\,N + 1.76\ \text{dB}$

MT-001 credits the analysis to Bennett’s 1948 Bell Labs paper and notes that although the true spectrum of quantization noise “is quite complex to analyze, the simplified analysis which leads to Eq. 9 is accurate enough for most purposes.” The one condition it repeats three times is the bandwidth: the noise is spread across dc to f_s/2, and the SNR is defined over that band.

Why the 1.76 dB has nothing to do with N

The 6.02 per bit is 20 log₁₀(2): every extra bit halves q and halves the noise. The 1.76 is 20 log₁₀(√(3/2)) — the ratio of a sine’s rms to a sawtooth’s, for equal peak amplitude. It is a property of the test signal, not the converter, and it is why the formula is quoted “for a full-scale sinewave”. A different waveform, or a signal below full scale, changes it; MT-003’s ENOB correction, below, is exactly that adjustment made explicit.

What “over dc to f_s/2” commits you to

The quantization noise has a fixed rms of q/√12 whatever the sample rate. Raise f_s and the same noise is spread thinner across a wider band; lower it and the noise concentrates. Two consequences follow, and they are the two things people most often get wrong.

The first is that the noise has a density. MT-001 states the noise is “spread more or less uniformly over the Nyquist bandwidth”, so the density is the rms divided by the square root of that bandwidth:

$e_n = \frac{q / \sqrt{12}}{\sqrt{f_s / 2}}$

For 12 bits across 2 V at 80 MSPS: q = 488 µV, e_rms = 141 µV, and e_n = 141 µV / √(40 MHz) = 22.3 nV/√Hz. That is the number to put beside an amplifier’s noise density when deciding which of the two dominates a signal chain — and it is a derived quantity, so the calculator labels it as one.

The second consequence is process gain.

Process gain: filtering buys SNR

If the signal of interest occupies a bandwidth BW narrower than f_s/2, and a digital filter removes everything outside it, the noise that was outside goes with it. MT-001 Eq 10:

$\text{SNR}_{BW} = 6.02\,N + 1.76 + 10\log_{10}\!\left(\frac{f_s}{2\,BW}\right)$

The tutorial’s example is a cellular base station digitising a 12.5 MHz band at 65 MSPS and filtering out individual 30 kHz channels:

process gain = 10 log(65 MHz / (2 × 30 kHz)) = 30.3 dB
ADC SNR      = 65 dB   (dc to fs/2)
in-band SNR  = 65 + 30.3                     = 95.3 dB   in each 30 kHz channel

Thirty decibels is five bits. Oversampling with digital filtering is the whole basis of sigma-delta converters, but as MT-001 notes it “can be used with any ADC architecture”, and it means the SNR on a datasheet is only comparable with another once both bandwidths are known.

The FFT noise floor is not the SNR

This is the section MT-001 titles “SNR, Process Gain, and FFT Noise Floor Relationships”, and it is the one to read twice:

Note that the average value of the noise floor of the FFT is approximately 107 dB below full-scale, but the theoretical SNR of a 12-bit ADC is 74 dB. The FFT noise floor is not the SNR of the ADC, because the FFT acts like an analog spectrum analyzer with a bandwidth of fs/M, where M is the number of points in the FFT. The theoretical FFT noise floor is therefore 10log10(M/2) dB below the quantization noise floor due to the processing gain of the FFT.

The mechanism is process gain again, applied by the measurement instead of by a filter. An M-point FFT has M/2 bins across dc to f_s/2, each f_s/M wide, and each bin sees only its own share of the noise:

12 bits, M = 4096:   floor = 74 + 10 log(4096/2) = 74 + 33 = 107 dB     MT-001 Fig 6
12 bits, M = 8192:   floor = 74 + 10 log(8192/2) = 74 + 36 = 110 dB     MT-003 Fig 2

Two practical rules fall out. The floor moves with M, so an FFT has to be long enough that the distortion products being looked for stand clear of it — for the 12-bit converter with a near-full-scale input, a spur at −110 dBc sits 3 dB below the 4096-point floor of 107 dB and is buried, and 9 dB above the 65 536-point floor of 119 dB, where it stands out. And averaging does not help: both tutorials say so explicitly, MT-003 that it “does not affect the average noise floor, it only acts to ‘smooth’ the random variations”. Averaging makes the floor look tidier at the same height.

What a real converter loses

An ideal converter has only quantization noise. A real one adds thermal noise, reference noise, differential nonlinearity and harmonic distortion, and MT-003 defines how the datasheet reports them.

SNR is measured from the FFT with the harmonics excluded — “in practice, it is only necessary to exclude the first 5 harmonics, since they dominate.” THD is the harmonics alone, root-sum-square. SINAD is everything but dc, harmonics and noise together, and the three are related by a root-sum-square of the power ratios:

$\text{SINAD} = -10\log_{10}\!\left(10^{-\text{SNR}/10} + 10^{-\text{THD}/10}\right)$

ENOB is then the SNR formula solved for N with SINAD in place of SNR, plus a correction for a test signal below full scale:

$\text{ENOB} = \frac{\text{SINAD} - 1.76 + 20\log_{10}\!\left(A_{FS} / A_{in}\right)}{6.02}$

MT-003 tabulates a real part, the AD9444, 14 bits at 80 MSPS with a 95.111 MHz input aliased into the first Nyquist zone:

SNR    = 73.42 dB
THD    = 86.31 dB
SINAD  = −10 log(10^−7.342 + 10^−8.631) = 73.20 dB        (tabulated: 73.20)
ENOB   = (73.20 − 1.76) / 6.02             = 11.87 bits
floor  = 73.42 + 10 log(8192/2)            = 109.5 dB      (tabulated: 109.67)

A 14-bit part delivering 11.87 effective bits at that input frequency is not a poor part; it is what 14-bit converters do at 95 MHz. The point of ENOB is that the number on the package is a word length, and the effective resolution is what the measurement returns.

When quantization noise stops being noise

The whole derivation rests on the error being uncorrelated with the signal, and MT-001 shows what happens when it is not. An ideal 12-bit converter sampled at exactly 40 times its 2.000 MHz input puts its quantization error into harmonics of the signal: the rms is still q/√12 and the SNR still 74 dB, but the worst harmonic sits at −77 dBc. Shift the input to 2.111 MHz and the same converter shows a random floor and a 93 dBc SFDR. The tutorial’s conclusion is a test-bench rule:

In order to accurately measure the harmonic distortion of an ADC, steps must be taken to ensure that the test setup truly measures the ADC distortion, not the artifacts due to quantization noise correlation. This is done by properly choosing the frequency ratio and sometimes by summing a small amount of noise (dither) with the input signal.

In a real system the input is a band of frequencies plus some system noise, which dithers the error for free. On a bench with a clean sine and a synthesiser locked to the sampling clock, it is the first thing to check when the harmonics look worse than the datasheet.

The clock sets a floor of its own

None of the above involves the sampling clock, and the clock can set the floor by itself. A sample taken t_j seconds early or late on a signal of slope dv/dt is wrong by t_j · dv/dt, and for a full-scale sine at frequency f that averages to an SNR of

$\text{SNR}_{jitter} = 20\log_{10}\!\left(\frac{1}{2\pi f\, t_j}\right)$

MT-031 gives the equation and one example: “if t_j = 50 ps rms, f = 100 kHz, then SNR = 90 dB, equivalent to about 15-bit dynamic range.” It is independent of N, and it falls 6 dB for every doubling of either the input frequency or the jitter. The same 50 ps at 10 MHz is 50 dB — eight bits — and a 16-bit converter behind that clock is a 16-bit converter in name only. MT-031 adds that the t_j to use is the root-sum-square of the clock’s own jitter and the converter’s internal aperture jitter, which is why it belongs in the same grounding tutorial as the clock-distribution rules.

Where the quantization and jitter figures are comparable, they combine the way noise powers do — the same root-sum-square MT-003 uses for noise and distortion — and the calculator reports the combined value beside the two parts.

Reading a datasheet without getting lost

Three things to establish before two converters can be compared.

• Which bandwidth. SNR over dc to f_s/2 is the definition; an in-band figure with process gain included can be 30 dB higher for the same part. The datasheet has to say, and often it says it in a footnote.
• Which quantity. MT-003: “A few ADC data sheets somewhat loosely refer to SINAD as SNR, so you must be careful when interpreting these specifications and understand exactly what the manufacturer means.” A figure that already includes the harmonics must not have THD added to it again.
• Which amplitude. SNR and SINAD are specified near full scale, typically 0.5 to 1 dB below it to avoid clipping. A figure taken further down needs MT-003’s correction before it becomes an ENOB.

Where the model stops being valid

• Uncorrelated error only. The white-noise picture fails when the sampling clock and the signal are harmonically related; the rms is unchanged but the spectrum is not.
• Full-scale sine. The 1.76 dB and the ENOB relation assume it. MT-003 Eq 2 corrects for amplitude, not for waveform.
• Ideal quantizer. Differential nonlinearity, missing codes, thermal and reference noise all lower a real converter below the line. They enter through the measured SNR, not the formula.
• Process gain needs the filter. The in-band SNR exists after digital filtering, not before; a converter alone has the Nyquist figure.
• The FFT floor is the instrument’s. It is where to compare a spur on a plot, and nothing else. A signal chain is designed to the rms noise and its density, not to the floor of whatever FFT was used to look at it.

The procedure

1. Ideal SNR from N. Note it is over dc to f_s/2.
2. Rms noise from the span: q/√12. Density from the sample rate: rms over √(f_s/2). Compare the density with the front end’s.
3. If the signal is narrower than Nyquist and a filter follows, add 10 log₁₀(f_s/2BW).
4. Take the datasheet SNR and THD at the working input frequency and amplitude; check which of SNR and SINAD is actually quoted.
5. SINAD from SNR and THD; ENOB from SINAD, corrected to full scale.
6. Jitter-limited SNR from the clock and the highest input frequency. If it is below the converter’s SNR, the clock is the specification.
7. For an FFT measurement, choose M so the floor sits well under the spurs being measured, and an input frequency that is not a sub-multiple of f_s.

The charge-bucket settling calculator handles the other half of driving a SAR — whether the input settles to half an LSB inside the acquisition window — with the same LSB the noise chain starts from, and the mixed-signal grounding article covers the layout that keeps the digital noise out of the floor calculated here.

Sources

• ADI, MT-001 — Taking the Mystery out of the Infamous Formula, “SNR = 6.02N + 1.76dB,” and Why You Should Care, W. Kester, Rev. A 10/08. The sawtooth model, Eq 1–9, process gain Eq 10 with the 65 MSPS / 30 kHz example, the correlation demonstration, and the 12-bit / 4096-point FFT floor.
• ADI, MT-003 — Understand SINAD, ENOB, SNR, THD, THD + N, and SFDR so You Don’t Get Lost in the Noise Floor, W. Kester, Rev. A 10/08. The definitions, ENOB Eq 1–2, the SNR/THD/SINAD relations Eq 3–14, the 8192-point floor, and the AD9444 example.
• ADI, MT-031 — Grounding Data Converters and Solving the Mystery of “AGND” and “DGND”, W. Kester, sampling-clock section, Eq 4 and its 50 ps example.