100nF

Why the crystal won't start

A Pierce oscillator fails in a small number of ways: not enough gain for the crystal's ESR, too much drive, the wrong load capacitance, or a layout that adds stray capacitance where it does the most harm. Each has a test.

By crystalsoscillatorspcb layout

An oscillator that does not start is a bad bug to get, because it usually does start — on the bench, at room temperature, on three of the five prototypes. Then it fails on one board in fifty in the field at −20 °C, and by then you are shipping.

The Pierce oscillator inside almost every MCU is a small analogue circuit with about four ways to be wrong. All four are checkable before you build.

−1MCU oscillator amplifiercrystal, rated for C_LC1CsXTALINC2CsXTALOUTC_L = (C1 + Cs) · (C2 + Cs) / (C1 + C2 + 2·Cs)with C1 = C2 = C: C = 2·C_L − Cs
Fig 1 — What the crystal actually sees. C1 and C2 are the parts you fit; Cs is everything else — pin, pad and trace — and it is in parallel with them, on both sides.

1. Not enough gain for the crystal you chose

The amplifier has to make up the crystal’s losses. Those losses are its equivalent series resistance, and the relationship is direct — from TI’s SNAA065:

The gain required by the oscillator amplifier is directly proportional to the ESR of the crystal at the oscillation frequency. Consequently, a higher relative ESR requires a higher gain in order for the oscillator to achieve startup.

That is why MCU datasheets specify a maximum crystal ESR, and why the number is frequency-dependent. TI’s LMK04000 family, for example, supports up to 100 Ω. Pick a crystal above your MCU’s limit and it may still start on the bench, with a warm board and a typical part, and fail on the corner.

The trap is that ESR is not a single number. It rises for smaller packages, it rises for tuning-fork 32.768 kHz parts (tens of kilohms is normal), and the datasheet figure is a maximum across the production spread. Design against the maximum.

The crystal load calculator runs AN2867’s gain-margin test — comparing your MCU’s transconductance against the critical value set by ESR, C₀ and the load — and the margin wants to be comfortably above 5. If it comes out at 2, the oscillator is not “marginal”, it is a field failure you have not met yet.

2. Too much drive, which is the opposite problem

Having established that you need gain, note that you can have too much. A crystal is a mechanical resonator being physically flexed, and the power it dissipates is

P = I²_RMS · ESR

TI are blunt about the consequence: overdriving a crystal will either damage the crystal or cause premature ageing. Ageing means the frequency drifts over months — so an overdriven oscillator does not fail, it slowly goes out of tolerance, which is a far more expensive bug than one that fails immediately.

Typical limits are around 100 µW for an MHz-range part and 0.5 to 1 µW for a 32.768 kHz tuning fork. That three-orders-of-magnitude gap is why watch crystals so often need a series resistor on the XTALOUT side to throttle the drive, and why the same layout that works at 8 MHz destroys a 32 kHz part.

Many MCUs have a configurable oscillator gain setting for exactly this reason. “Set it to maximum so it definitely starts” is a plausible-sounding decision that quietly damages the crystal.

3. The load capacitance is wrong, so the frequency is wrong

A crystal is trimmed at the factory to hit its nominal frequency when it sees one specific capacitance across its terminals — the rated C_L, printed on the datasheet as 8, 9, 12.5, 18 or 20 pF. Give it a different load and it runs at a different frequency. It still oscillates; it is just not the frequency you asked for.

What sets the load is not only the two capacitors you fitted. As SWRA372 puts it, the capacitors together with any parasitic capacitance in the PCB and the crystal terminals compose the total load. So:

C_L = (C1 + Cs) · (C2 + Cs) / (C1 + C2 + 2·Cs)

and with the usual C1 = C2 = C, the value to fit is C = 2·C_L − Cs, where Cs is the stray per side: the MCU’s pin capacitance (2–4 pF is normal) plus the pad and trace (another 1–2 pF).

Getting this wrong is not a subtle error. The calculator’s worked example — an 8 MHz part with C_L = 10 pF, where rounding to the nearest E12 value leaves the load half a picofarad high — pulls the frequency 22 ppm. For Bluetooth Low Energy and 802.15.4, the entire carrier tolerance budget is 40 ppm, and that budget also has to absorb the crystal’s own production tolerance, its temperature coefficient and its ageing. Half a picofarad of carelessness can eat most of it.

Which is also the answer to the question of why a radio’s frequency offset is out of spec when the crystal is within tolerance: the crystal probably is within tolerance, for the load it was specified with, and it was not given that load.

4. The layout adds capacitance where it hurts

An oscillator node is a high-impedance, small-amplitude analogue node sitting in the middle of a digital chip. Microchip’s AVR186 makes the vulnerability explicit: the circuit has a high input impedance outside the resonance frequency, which degrades its immunity when an electrical field is applied in its vicinity, and modern low-power designs restrict the oscillation level to within about a volt, increasing susceptibility further.

Their typical parasitics are worth memorising, because they are the same order as the capacitors you are fitting:

Parasitic Typical
XTALIN to ground 1 pF
XTALOUT to ground 2 pF
XTALIN to XTALOUT 0.5 pF

And their blunt note: parasitic capacitance will reduce gain margin. Keep this to an absolute minimum.

The rules that follow, all from AVR186:

  • Place the crystal and its capacitors close to the pins, and keep the whole network away from high-frequency devices and traces.
  • Keep clock lines and frequently switching signals as far from the crystal connections as possible — crosstalk disturbs a small sine.
  • Route XTALIN and XTALOUT far apart, to minimise the 0.5 pF between them.
  • The ground connection for the load capacitors must be short, and must avoid return currents from USB, RS-232, LIN, PWM and power lines. Sharing that ground with a switching return is a classic cause of a jittery clock.
  • Place the XTALIN capacitor first and closest to the XTALIN pin and ground.
  • Put a ground area under the oscillator, connected to the oscillator ground, and connect the crystal’s metal housing to it.
  • Use NP0/C0G load capacitors. They are low-leakage and stable across temperature; a class 2 dielectric here would make your load capacitance a function of temperature, and therefore your frequency too. (This is the one place where the DC bias and temperature behaviour of X7R is disqualifying rather than merely annoying.)
  • On a single-layer board, put a guard ring around the oscillator components and connect it to the oscillator ground pin.

The order to check things in

  1. Does it start cold? Freeze spray on the crystal is the cheapest corner-case test there is. ESR rises and gain falls; if it is marginal, this finds it.
  2. What is the gain margin on paper? ESR, C₀, load and the MCU’s transconductance. Below 5, fix it before building more boards.
  3. What is the drive level? Especially on 32.768 kHz. If there is no series resistor and no gain setting, measure the amplitude.
  4. What is the actual load? Add the strays, not just the capacitors. Then check the resulting frequency error against your whole ppm budget, including temperature and ageing.
  5. Probe it properly, or not at all. A 10× scope probe adds around 10 pF directly onto the node you are trying to measure — enough to stop a marginal oscillator, or to start one that would not otherwise run. Probe XTALOUT through a series resistor, or use an active probe, and treat any measurement at XTALIN as approximate.

That last one produces the most confusing hour in oscillator debugging: the circuit works whenever you look at it.

Sources