555 astable design: frequency, duty cycle and error

Three equations run the classic 555 astable, and the LM555 datasheet (SNAS548D) prints all three. The output is high for $t_1 = 0.693\,(R_A + R_B)\,C$, low for $t_2 = 0.693\,R_B\,C$, and the period is their sum. Everything else on this page is a consequence of one asymmetry inside them: the capacitor charges through $R_A$ and $R_B$ in series and discharges through $R_B$ alone.

That asymmetry has a consequence worth knowing before the first resistor is picked. The high time contains $R_A + R_B$ and the low time contains only $R_B$, so the high time is always the longer of the two. The classic astable cannot produce a 50 % duty cycle, or anything below it, at any resistor values. It approaches 50 % as $R_B$ grows without bound, and pays for every step closer with discharge current. The 555 timer calculator solves both directions of this and refuses the combinations that have no solution; this article is why it refuses them.

Where 0.693 and 1.1 come from

Neither constant is a fudge factor, and neither is specific to the 555. The comparators inside the part sit at $\tfrac{1}{3}V_{CC}$ and $\tfrac{2}{3}V_{CC}$ — the datasheet gives the threshold as $0.667 \times V_{CC}$ and the trigger as 1.67 V at a 5 V supply — so every timing interval is an RC exponential crossing between two fixed fractions of the supply.

Charging from $\tfrac{1}{3}V_{CC}$ toward $V_{CC}$ and stopping at $\tfrac{2}{3}V_{CC}$ takes

$t = RC \ln\!\left(\frac{V_{CC} - \tfrac{1}{3}V_{CC}}{V_{CC} - \tfrac{2}{3}V_{CC}}\right) = RC \ln 2$

and discharging from $\tfrac{2}{3}V_{CC}$ toward zero, stopping at $\tfrac{1}{3}V_{CC}$, takes $RC \ln 2$ as well. So 0.693 is $\ln 2$, printed to three places. The monostable’s 1.1 is $\ln 3$, because there the capacitor starts at zero instead of at a third of the supply:

$t = RC \ln\!\left(\frac{V_{CC} - 0}{V_{CC} - \tfrac{2}{3}V_{CC}}\right) = RC \ln 3$

Both roundings are harmless — 0.693 is 0.02 % below $\ln 2$ and 1.1 is 0.13 % above $\ln 3$ — but knowing they are logarithms is what lets every other question on this page be answered. Change the thresholds and the constants change with them; that is exactly what happens when the discharge pin fails to reach ground, several sections below.

The period does not contain the supply voltage

The most useful property of the topology falls straight out of the logarithm. Both the starting voltage and the target scale with $V_{CC}$, so the supply cancels inside the ratio and the period does not depend on it. The datasheet states the same thing twice, once for each mode: in the monostable, “since the charge and the threshold level of the comparator are both directly proportional to supply voltage, the timing interval is independent of supply”, and in the astable,

As in the triggered mode, the charge and discharge times, and therefore the frequency are independent of the supply voltage.

This is a first-order statement, not a guarantee. The datasheet’s own astable error line still allows 0.30 % per volt of drift with supply, and the saturation effect below is one of the reasons that number is not zero. But it means a 555 running from an unregulated supply keeps its frequency far better than a comparator-and-reference oscillator would, which is a large part of why the part survived fifty years.

Duty cycle and frequency are not independent knobs

Dividing the high time by the period gives

$D = \frac{t_1}{t_1 + t_2} = \frac{R_A + R_B}{R_A + 2R_B}$

Both $R_A$ and $R_B$ appear in both the period and the duty cycle, so there are two equations in two unknowns and no free choice left once frequency and duty are fixed. That is the useful way round: pick $C$, pick $f$ and $D$, and the two resistors are determined.

Solving them out, with $T = 1/f$:

$R_B = \frac{(1-D)\,T}{C \ln 2}, \qquad R_A = \frac{(2D-1)\,T}{C \ln 2}$

and the second of those is the whole story about 50 %. $R_A$ is positive only when $D > 0.5$. At exactly 50 % it demands $R_A = 0$, which shorts the supply to the discharge pin; below 50 % it demands a negative resistance. This is why the calculator rejects a target duty at or under half, rather than returning a value that would not work on a bench.

A worked example, end to end

Take $R_A = 6.8\ \text{k}\Omega$, $R_B = 3.3\ \text{k}\Omega$, $C = 100\ \text{nF}$ at 5 V — ordinary E24 values, nothing chosen to make the arithmetic tidy:

t_high = ln2 x (6800 + 3300) x 100e-9  = 0.7001 ms
t_low  = ln2 x 3300 x 100e-9           = 0.2287 ms
period = 0.7001 + 0.2287                = 0.9288 ms
f      = 1 / 0.9288 ms                  = 1076.6 Hz
duty   = 0.7001 / 0.9288                = 75.4 %

Round trip that through the printed constants instead of the logarithms and the frequency comes out 1076.9 Hz — 0.02 % higher, because 0.693 sits fractionally below $\ln 2$ — three orders of magnitude below the part’s own initial accuracy. The rounding in the datasheet is not what will be wrong with this circuit.

Choose the capacitor first

Frequency is inversely proportional to $C$ and to $R_A + 2R_B$ alike, so on a log plot the design space is a family of parallel lines and choosing $C$ selects which line you are on. That ordering matters because the resistors are the constrained variable and the capacitor is not: resistors are bounded below by the discharge pin’s current and above by the part’s threshold current, while capacitors are available across nine decades.

The practical rule is to pick the largest capacitor that keeps the resistors inside 1 kΩ–100 kΩ, and to prefer C0G/NP0 for anything whose frequency is supposed to stay put. A 100 nF X7R part is not a 100 nF part at temperature or under bias — see the DC bias capacitance loss that class 2 ceramics carry — and in a timing circuit that loss appears directly as frequency error, ahead of every term the 555’s own datasheet lists.

Getting to 50 % and below: the diode across RB

The standard fix puts a diode across $R_B$, anode at the discharge pin, so that charge current bypasses $R_B$ through the diode while discharge current still has to go through it. The two intervals become independent: $R_A$ sets the high time, $R_B$ sets the low time, and any duty cycle between the two extremes becomes reachable.

The diode is not free, and the usual textbook version of the modification — “now $D = R_A/(R_A + R_B)$” — is the version that fails on the bench. A silicon diode drops something like 0.6 V, and that drop comes off the charging asymptote: the capacitor is no longer heading for $V_{CC}$ but for $V_{CC} - V_F$. The high time becomes

$t_1 = R_A C \ln\!\left(\frac{V_{CC} - V_F - \tfrac{1}{3}V_{CC}}{V_{CC} - V_F - \tfrac{2}{3}V_{CC}}\right)$

which is no longer $\ln 2$ times anything. At 5 V with a 0.6 V drop, setting $R_A = R_B$ and expecting a square wave gets 57.6 % instead; equal times need $R_A \approx 0.74\,R_B$. The error shrinks as the supply rises, because $V_F$ is a fixed voltage subtracted from an amplitude that scales — which is the same reason a Schottky helps and a 12 V supply helps more.

What the discharge pin is being asked to do

The discharge pin is an open collector. The datasheet describes it as an “open collector output which discharges a capacitor between intervals (in phase with output)”, and at the instant the output goes low it has to sink whatever $\tfrac{2}{3}V_{CC}$ across $R_B$ demands. For the worked example that is 1.01 mA, which is nothing. Drop $R_B$ to 100 Ω at 15 V and it is 100 mA — half of what the part’s output stage is rated to source or sink, flowing instead through a pin that has no current rating at all. The 200 mA in the datasheet belongs to pin 3. The only thing SNAS548D says about pin 7 current is footnote (6) to the saturation specification:

No protection against excessive pin 7 current is necessary providing the package dissipation rating will not be exceeded.

That rating is 613 mW absolute maximum for the VSSOP, derated above 25 °C, and the pin itself is specified at just two points: 180 mV with 15 mA flowing at 15 V, and up to 200 mV with 4.5 mA at 4.5 V. Worked back through $\tfrac{2}{3}V_{CC}/R_B$, both of those points correspond to $R_B \approx 670\ \Omega$. Below that the pin is in territory the specification table does not cover, and the datasheet’s typical curves for it (Figures 9 and 10) show why that matters: the saturation voltage climbs from tens of millivolts at 1 mA to about a volt at 100 mA at 15 V, and the 5 V curve stops at around 30 mA.

This sets the lower wall of the design space, and it is the reason small resistors are not simply a way to reach high frequencies. Two things go wrong long before the package dissipation does:

• The saturation voltage stops being negligible. The next section is about what the two specified points — and the curve beyond them — do to the timing.
• The dissipation is real. Each cycle the energy the capacitor gives up is dissipated in $R_B$ and the discharge transistor, split in proportion to their voltage drops, so as the saturation voltage climbs the transistor’s share climbs with it. The LM555 in a VSSOP package has a junction-to-ambient thermal resistance of 204 °C/W — the same θJA-is-a-property-of-the-test-board problem every other small package has.

The error nobody budgets for: the discharge floor

Every derivation above assumed the capacitor discharges toward 0 V. It does not. It discharges toward the saturation voltage of the transistor on pin 7, and that changes the ratio inside the logarithm:

$t_2 = R_B C \ln\!\left(\frac{\tfrac{2}{3}V_{CC} - V_{SAT}}{\tfrac{1}{3}V_{CC} - V_{SAT}}\right)$

Put the datasheet’s 200 mV worst case into that at a 5 V supply and the low interval is 9.5 % longer than $\ln 2 \cdot R_B C$. At 15 V the same 200 mV costs 3.0 %, and with the typical 80 mV at 5 V it is 3.6 %. Those figures are for the low interval alone; the high interval charges toward $V_{CC}$ and is untouched, so on the period the error scales by $1 - D$. For the worked example, with $D = 75.4$ %, the 9.5 % becomes about 2.3 % of the period and the typical 80 mV about 0.9 % — the worst case is the whole of the 2.25 % initial accuracy the same datasheet quotes, spent on one mechanism.

The shape of that curve is the point. The error is a fixed voltage measured against a threshold that scales with the supply, so running a 555 at 5 V rather than 15 V roughly triples the timing error the discharge floor contributes. Two qualifications keep that honest. The 200 mV maximum is specified with 4.5 mA flowing into pin 7; the worked example sinks 1 mA, so its floor is lower, and 200 mV is an upper bound rather than a prediction. And the datasheet’s 2.25 % is not blind to the mechanism: footnote (4) says the timing error was tested at both 5 V and 15 V, with $R_A$ and $R_B$ down to 1 kΩ, so whatever saturation error exists under those conditions is already inside that figure. What the curve shows is how much of it this one mechanism can account for at 5 V, and why a circuit that sinks more pin 7 current than the test condition — a smaller $R_B$, or a larger capacitor at the same frequency — can see more than the datasheet quotes. If the duty cycle of a 5 V 555 measures a few per cent away from the calculated value, this is a likely place it went, and no amount of resistor precision will recover it.

The error budget the datasheet does publish

For the astable, SNAS548D specifies, over $R_A, R_B = 1\ \text{k}\Omega$ to 100 kΩ with $C = 0.1\ \mu\text{F}$:

Term	Astable	Monostable
Initial accuracy	2.25 %	1 %
Drift with temperature	150 ppm/°C	50 ppm/°C
Accuracy over temperature	3.0 %	1.5 %
Drift with supply	0.30 %/V	0.1 %/V

Two things are worth reading off that table. First, the astable is roughly twice as bad as the monostable on every line, because it uses both comparators and both thresholds instead of one. Second, the numbers are per cent, not parts per million: over 0 to 70 °C with a ±5 % supply the total band reaches ±3.0 % at the 70 °C end — 25 °C is not the middle of the range, so the cold end stops at ±2.7 % — matching the datasheet’s own “accuracy over temperature” line, and that is before the capacitor’s own tolerance and temperature coefficient join it.

For scale, a 20 ppm crystal is a thousand times better, and what it takes to get a crystal to start is the price of that. A 555 is a fine choice for a blinker, a PWM ramp, a watchdog kick or a delay; it is the wrong choice for anything whose frequency has to agree with another device’s — the baud rate error calculator shows how little margin an asynchronous link leaves before framing fails.

The upper wall: threshold current and 20 MΩ

At the other end of the resistance range the limit is leakage. The datasheet specifies a threshold current of 0.25 µA maximum, and attaches an unusually direct footnote to it:

This will determine the maximum value of RA + RB for 15 V operation. The maximum total (RA + RB) is 20 MΩ.

The reasoning is that the current flowing into the threshold pin has to be small compared with the current charging the capacitor through $R_A + R_B$; at 20 MΩ and 15 V, the charging current is well under a microamp and the comparator’s own input current is a significant fraction of it. Past that, the timing stops being set by the RC at all.

So the astable’s usable design space has a hard wall at each end — the discharge current on the left, 20 MΩ on the right — and a narrower strip in the middle, 1 kΩ to 100 kΩ, which is the only region where the timing error figures above were actually measured. Designing outside that strip is allowed; quoting those error figures while doing it is not.

The monostable, and its one trap

In the monostable, the same part becomes a one-shot: a trigger falling below $\tfrac{1}{3}V_{CC}$ releases the discharge transistor and drives the output high, and the pulse ends when the capacitor reaches $\tfrac{2}{3}V_{CC}$ — $\ln 3 \cdot R_A C$ later. The datasheet’s own example is $R_A = 9.1$ kΩ with $C = 0.01\ \mu\text{F}$, which computes to 100.0 µs.

The trap is retriggering. During the timing cycle, a further trigger pulse has no effect — but only conditionally:

During the timing cycle when the output is high, the further application of a trigger pulse will not effect the circuit so long as the trigger input is returned high at least 10 μs before the end of the timing interval.

A trigger input still sitting low when the interval expires holds the output high past its calculated width. That makes a bare pushbutton on the trigger pin a poor idea for any pulse shorter than the time a finger stays down, and it is why the datasheet’s own LED example wires the button through a pull-up and relies on the pulse being five seconds long. An RC differentiator on the trigger input fixes it properly.

The pins nobody wires up, and why they bite

Two pins are routinely left floating on a schematic that then behaves oddly.

Reset, pin 4. A low on it disables the timer. The datasheet is explicit: “when not used for reset purposes, it should be connected to VCC to avoid false triggering”. A floating reset pin on a board with a switching supply nearby is a board that stops oscillating intermittently.

Control voltage, pin 5. It is the $\tfrac{2}{3}V_{CC}$ reference brought out, and the datasheet notes an external voltage there “can also be used to modulate the output waveform” — which is the whole basis of 555 pulse-width modulation. Left unconnected it is a high-impedance node sitting at the reference, wired directly into a comparator input: exactly the arrangement guard rings exist for. The conventional 10 nF to ground on pin 5 is not decoupling in the supply sense; it is holding a comparator threshold still.

The supply pin needs the usual treatment for a different reason. The output stage can source or sink 200 mA and switches in about 100 ns, and that current has to come from somewhere in that time. This is the ordinary case for a 100 nF close to the pin, placed with the via right at the pad — a 555 driving a load hard enough to matter is a 555 that can disturb its own thresholds through the supply.

Where the 555 stops being the right part

A short list, since the failure modes are all predictable from the above:

• A duty cycle at or below 50 % — impossible without the diode, and with the diode the forward drop has to be in the arithmetic.
• Frequency accuracy better than a few per cent — the datasheet says 2.25 % before the capacitor is even considered.
• Long timing at low current — the 20 MΩ ceiling caps the resistance, so long intervals need large capacitance, and large capacitance at low leakage is electrolytic, whose own leakage then sets the interval.
• Sub-microsecond pulses — the output’s 100 ns rise and fall are a significant fraction of the interval, and the propagation delay through the comparator is not in any of the equations.
• A clean supply — 200 mA switching in 100 ns is a noise source sharing a rail with whatever else is on the board.

Everything else it does well, cheaply, and with parts that have been in distribution since 1972. Work the values out with the 555 timer calculator, which solves in both directions and flags the resistor range the datasheet’s error figures actually cover, then check the duty cycle against Fig 4 before ordering the board.