Switch-node ringing: measure it, then size the snubber

Two scope readings give the loop inductance and the parasitic capacitance. From those the snubber values follow, and so does the reason to fix the layout first.

A synchronous buck’s switch node overshoots and rings every time the high-side FET turns on, and the question is only whether it stays under the low-side FET’s absolute maximum. TI’s SLYT465 (Controlling switch-node ringing in synchronous buck converters) measured a 1.1 V / 20 A converter ringing to 23.4 V from a 12 V input against a 30 V FET — 78 % of absolute maximum, on a competent layout, with nothing wrong.

The useful thing about that ringing is that it tells you the two parasitics producing it. Two oscilloscope readings and two square roots give the loop inductance and the capacitance it is resonating with, and from those the snubber values follow directly. This article works through that identification and then through what each remedy costs, because the cheapest remedy is not a component at all. The RC snubber calculator carries the same two formulas, and integrates the resulting network so a resistor can be judged by the overshoot it leaves rather than by the label on the equation.

A synchronous buck power stage with the high-slew-rate loop highlighted: input capacitor, high-side FET and low-side FET. The stray inductance of that loop and the output capacitance of the low-side FET form the resonant circuit that rings. — Fig 1 — The circuit that rings, which is not the whole converter. SLYT682 identifies the loop through the input capacitor and both FETs as the one with high current slew rate, and notes that the output inductor's own parasitics are "essentially benign" because its current barely changes. The ring is that loop's inductance against the low-side FET's output capacitance.

What is ringing, and what is not

Not everything in the converter participates. TI’s SLYT682 (Reduce buck-converter EMI and voltage stress by minimizing inductive parasitics) identifies the loop that matters:

the loop shaded in red and labeled “1” in Figure 1 is designated as the high-frequency switching power loop (or “hot” loop)

and then explains why the output side is exempt:

In contrast, the current flowing in the inductor, LF, is largely DC with superimposed triangular ripple. The rate of change of the current is inherently limited by the inductor and any parasitic inductance contributed by the series connections is essentially benign.

So the resonant circuit is the stray inductance of the input-capacitor-to-FETs loop, ringing against the low-side FET’s output capacitance. The buck converter layout article is about finding and shrinking that loop; this one is about what to do once it is as small as it is going to get.

SLYT465’s account of how the energy gets there is worth reading closely, because it explains why the ring appears at high-side turn-on rather than at turn-off:

Strong gate drivers and a fast-switching FET allow the low-side FET to be turned off quickly. … energy remains in the parasitic drain and source inductances of the low-side FET. After a fixed dead time, the high-side FET turns on, and the energy from the low-side and high-side FETs’ parasitic inductances appears as an LC ringing waveform on the switch node.

Switch-node voltage after the high-side FET turns on, overshooting well past the input voltage and ringing down over several cycles, with the FET absolute maximum drain-source rating marked just above the first peak. — Fig 2 — What the scope shows, evaluated from the series RLC formed by the loop inductance and the FET's output capacitance. SLYT465's test circuit rang to 23.4 V from a 12 V input against a 30 V FET rating — 78 % of absolute maximum, on a good layout, with nothing wrong.

Identifying L and C from two measurements

There is one equation and two unknowns, so one measurement is not enough. SLYT465’s method makes the second measurement with a component you already have in a drawer:

Once the frequency is determined, a capacitor is put in parallel with the low-side FET to change the ringing frequency to half the original value. When the frequency is half the original value, the parallel capacitor is equal to three times the parasitic capacitance of the original circuit.

The arithmetic behind it is one line. Frequency goes as $1/\sqrt{C}$ , so halving it requires four times the total capacitance; if the total is now $4C_{par}$ , the part you added is $3C_{par}$ . Then the inductance follows from the original frequency:

$C_{par} = \frac{C_{added}}{3}, \qquad L = \frac{1}{(2\pi f_0)^2\,C_{par}}$

Working an example: a switch node rings at 100 MHz, and adding 1 nF across the low-side FET brings it to 50 MHz. Then $C_{par} = 333$ pF and $L = 7.6$ nH — an entirely ordinary loop inductance for a compact power stage, and, more to the point, a number that a better layout reduces.

Ringing frequency plotted against the capacitance added across the low-side FET, falling as the inverse square root of total capacitance. The point where the frequency has halved is marked, and at that point the added capacitance is three times the parasitic one. — Fig 3 — SLYT465's identification trick, and why it works. Frequency goes as 1/√C, so halving it needs four times the total capacitance — which means the capacitance you added is three times the parasitic capacitance you were trying to measure. Here 1 nF halves 100 MHz to 50 MHz, so C_par is 333 pF.

Loop inductance plotted against measured ringing frequency on log axes, with one line for each of several parasitic capacitances. Higher ringing frequencies imply smaller loop inductances. — Fig 4 — The second half of the identification: with the frequency and the capacitance both known, the loop inductance follows from L = 1/((2πf₀)²C). The worked case lands at 7.6 nH, which is an ordinary figure for a compact power stage and is worth knowing because it is the number a better layout reduces.

The resistor, and why √(L/C)

With both parasitics known, SLYT465 gives the resistor directly:

The resistor to critically damp the circuit is calculated from the equation R = √(L/C).

That quantity is the characteristic impedance of the ringing circuit. A resistor equal to it is matched to the resonance: too small and it is close to a short across the capacitor, so almost no voltage develops across it and it absorbs little; too large and almost no current flows through it, so it absorbs little again. For the worked case that is 4.8 Ω.

Simulating the actual topology — the loop inductance in series with the FET capacitance, and the snubber’s resistor and capacitor in parallel with that — confirms the shape of the trade. With no snubber the node reaches 22.7 V from a 12 V step. That number says little about the parasitics: a step into a lightly damped LC nearly doubles whatever L and C are, and the exact peak is set by the loop resistance assumed (0.35 Ω here), so its closeness to SLYT465’s measured 23.4 V is not a check on the model. What the simulation is for is the resistor comparison. At one fifth of $\sqrt{L/C}$ it reaches 18.9 V; at $\sqrt{L/C}$ , 16.0 V; at eight times it comes back up to 20.7 V.

SLYT465 states the direction of the two knobs plainly, and both are worth remembering because they point opposite ways:

Increasing the resistance results in an underdamped system, which allows more ringing but decreases power dissipation. Increasing the capacitance reduces the ringing but increases power dissipation.

The same ringing waveform drawn for four snubber resistances: none, one fifth of critical, critical, and eight times critical. The critical value removes the ring in about one cycle while too large a resistor leaves it almost undamped. — Fig 5 — Why R = √(L/C) is the value. Too small and the resistor is a short across the ring, doing little; too large and it stops carrying current at all, which is why the ringing comes back at high resistance. For the worked case critical damping is 4.8 Ω.

What the snubber costs, exactly

The capacitor is charged to the input voltage and discharged to zero on every switching cycle, so its energy is dissipated twice per cycle in the resistor and the switches:

$P = C\,V_{in}^2\,f_{sw}$

The resistor value does not appear. It decides where the heat goes and how the ringing is damped, not how much energy is lost. For the worked case — 1 nF at 12 V and 600 kHz — that is 86 mW. For SLYT465’s own 2200 pF at the same voltage and frequency it is 190 mW, and the efficiency columns in its table imply an extra loss of about 145 mW at 12 V, which is the same quantity to within the precision of a two-significant-figure efficiency reading.

Two consequences follow, and both are about where the loss falls rather than how large it is.

It scales with the square of the input voltage. A snubber tuned at 12 V dissipates four times as much at 24 V. On a wide-input converter that is a thermal question, not just an efficiency one.

It does not scale with load. The 86 mW is drawn whether the converter is delivering 20 A or nothing, so at light load the snubber is most of the loss. That is why SLYT465’s conclusion notes that an RC snubber “has low efficiency at light loads”, and why a snubber is a poor choice for anything that spends its life idling.

Snubber dissipation plotted against snubber capacitance for three input voltages, all straight lines through the origin, with the worked case marked. — Fig 6 — The bill, and it is exact rather than estimated. The capacitor is charged to the input voltage and discharged every switching cycle, so it dissipates C·V²·f regardless of the resistor value — the resistor decides where the heat goes, not how much. At 1 nF, 12 V and 600 kHz that is 86 mW.

Fix the loop before fixing the symptom

How much the overshoot falls with the loop inductance depends on what is taken to excite it, and the step-driven simulation above is the wrong model for that question: it holds the excitation at $V_{in}$ and lets the ring nearly double it, so its peak hardly moves when $L$ changes. SLYT465’s account is the energy one — while the low-side FET carries the load current, its parasitic inductance stores $E = \tfrac{1}{2}LI^2$ , and that energy “appears as an LC ringing waveform on the switch node” when the high-side FET turns on. Handed to $C_{par}$ , it produces an overshoot of $I\sqrt{L/C}$ : the commutating current times the ringing circuit’s characteristic impedance. At a fixed current and a fixed FET capacitance the overshoot therefore falls as the square root of the loop inductance. Halving the loop inductance removes 29 % of the overshoot, costs nothing, and dissipates nothing. SLYT682 reads the same event as $L\,di/dt$ — at a slew rate that “may exceed 5 A/ns, just 2 nH of parasitic inductance results in a voltage overshoot of 10 V” — under which halving $L$ halves the overshoot, so 29 % is the conservative end of the two. A snubber that achieved the same reduction would be burning power on every cycle for the life of the product.

That is the whole argument for doing the layout work first, and the numbers make it concrete: a 3 mm run of ordinary PCB trace is roughly 3 nH, so the difference between an input capacitor placed against the FET pins and one placed 5 mm away is most of the loop inductance in a modern power block.

The order matters for a second reason. SLYT465 is explicit that the remedies below can be undone by the thing they are compensating for:

These techniques can be nullified by poor power-supply layout, so it is important to take this into consideration as well.

Overshoot relative to its value at the worked-case loop inductance, plotted against loop inductance under the stored-energy model, in which the overshoot is the commutating current times the square root of L over C. The curve is a square root, so halving the loop inductance removes twenty-nine per cent of the overshoot. — Fig 7 — Why layout comes before any remedy. Under SLYT465's energy picture — ½LI² stored in the loop's parasitic inductance at the commutating current, then handed to C_par — the overshoot is I·√(L/C), the current times the ringing circuit's characteristic impedance, so at a fixed current and a fixed FET capacitance it falls as the square root of the loop inductance. The step-driven waveforms of Fig 2 and Fig 5 cannot show this: they hold the excitation at V_in whatever L is. Halving the loop takes 29 % off the overshoot, costs nothing, and dissipates nothing — a snubber achieving the same would burn power on every cycle for the life of the product. The absolute voltage depends on how much current is actually commutating, which is why this axis is relative.

The three remedies, and what each costs

SLYT465 measured all three on the same board, tuned each to bring the 12 V case under 20 V, and published the result. That comparison is the most useful part of the note.

Boot resistor. A resistor in series with the bootstrap capacitor slows the high-side turn-on and nothing else, so it is the cheapest in efficiency — 87.2 % falling to 86.8 % at 12 V. Its limit is the bootstrap capacitor’s own recharging: SLYT465 warns that if the resistor is too large, “the boot capacitor may not get fully charged in each cycle. In this case, the gate driver would not have sufficient voltage to keep the high-side FET on and could turn off in the middle of the cycle.” The capacitor only has to replace the gate charge, so the comparison to make is $R_{boot}C_{boot}$ against the off-time. SLYT465 gives the resistor but not the capacitor, so take a typical 100 nF: 6.8 Ω with 100 nF is 680 ns against a 1.50 µs off-time at 10 % duty, which is comfortable, and against 830 ns at 50 % duty, which is not.

High-side gate resistor. The same idea, but in series with the gate, so it is in the discharge path too and slows turn-off as well. That is why it is the most expensive: 87.2 % down to 85.2 %, two full points.

RC snubber. The only one that changes the ringing frequency as well as its amplitude, which matters if the problem is an EMI limit at a particular frequency rather than a voltage rating. At full load it sits between the other two; at light load it is worse than either.

Bootstrap capacitor recharge time plotted against boot resistance, against the available off-time at two duty cycles. Past a few tens of ohms the capacitor cannot recharge within the off-time. — Fig 8 — The limit on the cheapest remedy. A boot resistor slows the high-side turn-on only, so it costs the least efficiency — SLYT465 measured 87.2 % falling to 86.8 %, against 85.2 % for a gate resistor. But the same resistor sits in the bootstrap capacitor's charging path, and SLYT465 warns that if it is too large "the boot capacitor may not get fully charged in each cycle". The capacitor only has to replace the gate charge each cycle, so the comparison that matters is R·C against the off-time, not a full charge.

Measured peak switch-node ringing for four circuit variants at three input voltages, showing that all three remedies reduce the ringing at every input, but that at the highest input none of them holds the node under the 20 volt target and the snubber is slightly worse than the boot resistor. — Fig 9 — SLYT465's table 1, as published: peak ringing on a 1.1 V / 20 A, 600 kHz converter. All three remedies were tuned to bring the 12 V case under 20 V. Look at the 16 V column — the snubber, tuned at 12 V, still helps there (23.7 V against a 28.3 V baseline) but is nowhere near 20 V and is marginally worse than the boot resistor's 22.6 V, which is the argument for tuning at the worst-case input.

Full-load efficiency for the same four circuit variants at three input voltages, showing the gate resistor costing the most efficiency and the boot resistor the least. — Fig 10 — What each remedy costs, from the same table. The gate resistor is the most expensive because it slows turn-off as well as turn-on; the boot resistor is the cheapest because it only affects turn-on. The snubber sits between them at full load — and is worse than either at light load, because its dissipation does not scale with the load.

Tune at the worst case, not the nominal

The 16 V column of that table is the part to read twice. All three remedies were optimised at a 12 V input. At 16 V the snubber gives 23.7 V against a baseline of 28.3 V — better, but not under 20 V, and in fact marginally worse than the boot resistor’s 22.6 V. The overshoot grows with the input voltage because the step the loop is excited by grows with it, so a remedy tuned at nominal input is a remedy tuned at the wrong point.

Note also what the baseline row says about the design itself: 28.3 V at a 16 V input, against a 30 V FET. Without any remedy at all, that converter has 1.7 V of margin on a device rating, before temperature, before tolerance, and before a transient on the input rail. That is the situation the article is about, and it is not unusual.

The procedure

A decision sequence: shrink the loop, then check whether the overshoot still exceeds the rating, then choose between a boot resistor, a gate resistor and a snubber according to which cost matters. — Fig 11 — The order, and the reason for it. The first step costs nothing and is the only one that reduces the energy in the ring rather than dissipating it. Everything after it is a trade of efficiency for margin, and SLYT465's own conclusion is that "the best approach may even be a combination of all three".

Four numbered steps for sizing an RC snubber: measure the ringing frequency, add capacitance until it halves, compute the loop inductance, and compute the resistance from the square root of L over C. — Fig 12 — The whole snubber procedure, which is two scope measurements and two square roots. The measurements and both formulas are SLYT465's; the 3–4 × C_par rule of thumb for the capacitor is not in the note, which says only that more capacitance damps more at more dissipation and used 2200 pF with 1 Ω. The numbers are this article's worked case.

Shrink the power loop first. Input capacitor against the FET pins, its return on the layer immediately below, no vias inside the loop. This is the only step that reduces the stored energy rather than dissipating it.
Measure at the highest input voltage, with a probe that can see the ringing — a ground clip will invent some of what you are looking at, which is a separate problem with its own article.
Identify the parasitics: note $f_0$ , add capacitance across the low-side FET until the frequency halves, then $C_{par} = C_{added}/3$ and $L = 1/((2\pi f_0)^2 C_{par})$ .
Choose the remedy by which cost matters. Boot resistor if efficiency does and the duty cycle is low; gate resistor if turn-off ringing also needs controlling; snubber if the ringing frequency itself is the problem.
Size and check: $R = \sqrt{L/C}$ as a starting value, $C$ three to four times $C_{par}$ , then compute $CV^2f$ and decide whether that loss is acceptable at light load as well as full load. The RC snubber calculator does all four steps and shows the peak each resistor leaves.
Re-measure across the whole input range and at temperature. SLYT465’s own conclusion is that “often, the best approach may even be a combination of all three circuits” — which is a way of saying that none of them is large enough on its own to rescue a loop that should have been smaller.