Buck converter PCB layout: find the hot loop first

The decision rule for a buck converter layout fits in one sentence: draw the current loop for each switch state, subtract one from the other, and shrink what remains before placing anything else. The loop left over after the subtraction — input capacitor, high-side FET, low-side FET or diode, back through ground — is the only path whose current is chopped between full load current and zero at every switching edge. Its area is the antenna, and its inductance is the spike generator.

That is why TI’s placement procedure starts where it does. In SLYT614, the five-step layout guide for step-down converters, the input capacitor is placed and routed before any other component, and everything after it is ordered by how much it can still go wrong. This article walks the same five steps, but with the reasoning from AN-1149 underneath each one, so the rules survive contact with a board the application note never saw.

Layout is part of the circuit

The schematic below is the power stage of SLYT614’s worked example, a TPS62130A stepping 12 V down to 3.3 V through a 2.2 µH inductor, with 10 µF at the input and 22 µF at the output.

Nothing on a schematic has an area. Every net is an ideal node, every connection is free, and the circuit works. On the board, each of those nets becomes a loop of copper with an inductance proportional to the area it encloses, and some of those loops carry currents with nanosecond edges. The parasitic inductance is a component you place — the only question is how big you make it. AN-1149 lists the symptoms of getting it wrong: loss of regulation at high output current, excessive noise on the output and switch waveforms, and instability — problems that get worse at high current and at large input-to-output differentials.

The way to see which loops matter is to trace the current in each of the two switch states separately.

The on-state loop

While the high-side FET conducts, current flows from the input capacitor and the input supply through Q1, out of the SW node, through the inductor into the output capacitor and the load, and back along ground.

During this state the inductor current ramps up, because the voltage across it is V_IN − V_OUT. Note the direction the loop circulates; it will matter in a moment.

The off-state loop

When Q1 turns off, the inductor current does not stop — inductor current never stops abruptly, which is the entire operating principle. It commutates into the low-side FET (or the diode, in a non-synchronous converter) and circulates from ground up through Q2, through the inductor, into the output and back.

The input capacitor and the high-side FET now carry nothing. AN-1149 makes a placement rule out of exactly this two-state picture:

Place the power components so that during each of the two states the current loop is conducting in the same direction. This prevents magnetic field reversal caused by the traces between the two half-cycles and reduces radiated EMI.

Both loops above circulate the same way. Keep them doing that on copper: a placement that forces the off-state current to curl backwards through shared traces reverses the magnetic field around those traces once per cycle, and the board radiates the reversal.

Subtract the loops: the hot loop

Overlay the two loops and cancel the shared path. The inductor, the output capacitor and the load carry nearly the same current in both states — the inductor current is continuous — so the whole right-hand side of the circuit drops out of the difference. What remains is small and vicious:

C_IN → Q1 → Q2 → ground → C_IN. At every switching edge, the current in this loop steps between the full inductor current and zero. Everywhere else the current changes slowly, at the inductor’s ramp rate; here it changes as fast as the FETs can switch. The di/dt lives here, and only here — which is why this path is worth a name. Call it the hot loop.

Two properties of the hot loop set the two failure modes:

• Its inductance turns the current step into a voltage spike, $v = L\,\frac{di}{dt}$ which appears across the FETs and the IC’s supply pins. SLYT614 is blunt about the consequence — the spikes from routing inductance in this path “can lead to IC failure”.
• Its area makes it a magnetic-loop antenna driven at the switching frequency and every harmonic the edges contain. The high-frequency spikes on the output rail — the part of the ripple that more capacitance never fixes — are this loop talking.

Both scale with geometry, not with component choice. A perfect capacitor in a big loop is a worse filter than an ordinary capacitor in a tiny one, which is the same lesson the decoupling measurements in the via is the decoupling taught at 40 dB scale.

What the waveforms say

The claim that only the input branch carries chopped current is worth computing rather than asserting. In steady state the volt-seconds across the inductor balance, so the ideal duty cycle at SLYT614’s operating point is $D = \frac{V_{OUT}}{V_{IN}} = \frac{3.3}{12} \approx 0.275$ and integrating the voltage across the inductor over two switching periods gives the currents below.

The inductor current is a continuous triangle: its loop needs copper wide enough for the RMS current, and no drama beyond that. The input-branch current is that triangle gated by the switch: it follows the rising ramp while Q1 conducts and drops to zero the instant Q1 opens, so the falling ramps never appear in it at all. Those vertical edges are the di/dt that the hot loop’s inductance converts into spikes. No filter downstream removes them; only shrinking the loop does.

Step 1: the input capacitor is the whole game

SLYT614 opens its procedure with a sentence that deserves quoting in full:

The input capacitor is the single-most important component for reliable operation of any step-down converter. As such, it should be the first component placed in the layout after the IC. Route the capacitor to the IC immediately after it is placed, so that nothing else can be routed in its path.

And the reason, in the same step:

Extra parasitic inductance between the input capacitor’s terminals, both power and ground, and the IC’s PVIN and PGND terminals creates excessive voltage spikes due to the switching action from V = L × dI/dt. This can lead to IC failure.

The input capacitor is the local terminal of the hot loop: it is what supplies the current step so the input traces upstream do not have to. It can only do that if the loop it closes is small. Place it against the PVIN and PGND pins as close as the manufacturing rules allow, and connect it with copper shapes, not traces — SLYT614’s instruction is that planes connect the capacitor’s terminals to the IC’s, because a wide, short connection minimises the trace inductance.

The bad version on the right is not a caricature; it is what happens by default when the input capacitor is placed with the other passives after the interesting routing is done. Every millimetre of that detour is series inductance inside the loop that carries the fastest current on the board. AN-1149 says the same thing from the supply’s point of view: a small ceramic input capacitor belongs as close to the VIN pin as possible, to give the IC’s internal rail a clean supply, and surface-mount parts beat leaded ones because leads are antennas.

Placement order is priority order. The reason step 1 exists as a step — not merely a rule — is that the first component routed claims the shortest path, and every later component has to route around it. Do it first and the loop is small forever; do it fifth and something else owns the space.

Vias feed the loop; they never sit in it

The input voltage and ground usually arrive on inner planes, so vias have to connect them — but where the vias go decides whether they help or hurt. SLYT614’s placement is specific: put the system vias outside the circuit, not between the input capacitor and the IC, so they do not obstruct the critical routing; put vias at the input and output capacitors’ ground terminals; and put the ground vias for heat directly under the exposed pad, where they conduct the IC’s heat into the board.

For sizing the connection to the system, SLYT614 gives the rule of thumb:

A good rule of thumb for the number of vias necessary is to use one via per amp of current flowing. However, more is better if room allows.

AN-1149’s figure for plane transitions is denser — one standard via per 200 mA where a trace must carry significant current from one plane to another. The via calculator turns a specific drill and plating into an actual current and resistance figure, which is the honest way to reconcile the two rules for your stackup. Either way the principle is the same: vias in parallel, outside the loop, feeding it; never a lone via in series inside it.

Step 2: the SW node, and how much copper it deserves

The hot loop is the di/dt problem. The SW node is the dv/dt problem.

Since the SW-node voltage swings from the input voltage to ground with very fast rise and fall times, it is the main generator of EMI in a SMPS.

That is SLYT614’s step 2, and it comes with the clearest mental model in the whole article:

All copper connected to the SW node is one plate of a parasitic capacitor, whose other plate is each node in the circuit. This capacitor is a noise coupling path.

Every square millimetre of SW copper couples the full 12 V swing, at the edge rate of the FETs, capacitively into everything nearby. So the SW node gets exactly enough copper to carry the inductor current and connect the pins — and no more. Place the inductor as close to the IC as possible, and rotate it as needed to keep the SW shape small and the path to the output capacitor easy.

There is a real tension here, because SW copper also spreads heat, and a converter using the PCB as its heatsink — which AN-1149 endorses as often eliminating a separate heatsink — wants area. The resolution is to spend the area on nets that do not swing: ground, V_IN, V_OUT, the exposed pad. The SW node is the one net where copper is not free.

If an RC snubber is needed to slow the SW edges for EMI, step 2 is when it goes in, directly across SW and PGND where its own loop is shortest — with the caveat SLYT614 attaches, that slowing the edges buys EMI margin at the price of switching-loss efficiency.

Step 3: the output capacitor closes the path

The output capacitor is the last of the power components, placed to minimise the distance from the inductor back to power ground. Misplace it and the symptom is not spikes but poor output-voltage regulation — its loop carries the continuous triangle, not the chopped edge, so the penalty for length is ripple and regulation rather than EMI.

One instruction in step 3 is easy to skim past and expensive to ignore:

Finally, no vias should be used to route these components, because vias add significant inductance to the trace.

The power path — input capacitor, FETs, inductor, output capacitor — stays on one layer. The case that tests the rule sits in SLYT614’s special considerations: on many wafer chip-scale packages — the TPS62360 is the example given — the pinout puts the SW pin between VIN and PGND, so an input capacitor placed by step 1 blocks access to SW. SLYT614’s preferred fix is not a via: route the SW pin underneath the input capacitor on a thin trace. The trace is narrow because it squeezes between the capacitor’s terminals, but it is also very short, which keeps the SW node small — step 2 applied literally. Only if such a trace is not possible does SLYT614 allow vias from the SW pin to the inductor, and it says why they are tolerable rather than good: the longer routing merely creates additional EMI, and the vias’ inductance is not critical because it is in series with the inductor’s own inductance. Either way, SLYT614 rates vias in this path a better choice than moving the input capacitor out of its ideal location. Inductance in series with L is nearly free; inductance in series with C_IN is a spike. Same via, different loop, opposite verdict.

The remote-sense connection gets its priority here too: the TPS62130A’s VOS pin is, in SLYT614’s words, the most critical small-signal connection, routed short and direct to the output capacitor before the other signals are even considered, so that a noisy sense point does not turn into regulation jitter.

Step 4: the feedback trace is the victim

Everything so far generates noise; the feedback divider receives it. The FB node is the highest-impedance consequential net on the board — hundreds of kilohms in the example circuit (1.21 MΩ over 383 kΩ) — and whatever couples into it is regulated into the output as if it were real.

AN-1149 gives the routing rule and, unusually, ranks the trade-offs inside it:

Try to run the feedback trace as far from the inductor and noisy power traces as possible. You would also like the feedback trace to be as direct as possible and somewhat thick. These two sometimes involve a trade-off, but keeping it away from inductor EMI and other noise sources is the more critical of the two.

And the escape hatch when the top layer offers no quiet route:

It is often a good idea to run the feedback trace on the side of the PCB opposite of the inductor with a ground plane separating the two.

SLYT614’s step 4 adds the placement half: the divider and the other small-signal parts — soft-start capacitor, AVIN decoupling — sit close to the IC with short, direct routing, keeping the FB node physically small so there is less of it to couple into. Digital signals like enable and power-good come last; they are driven from low impedance and can take almost any route.

Step 5: ground is two nets, joined once

Ground under a switching converter is not one node. The chopped return current of the hot loop flows in it, and any impedance that current shares with the feedback divider’s reference turns the hot loop’s IR and L·di/dt drops into an error voltage in series with FB.

The scheme in SLYT614’s step 5: keep one ground for the power components, which are noisy, and a separate ground for the small-signal components, which are quiet, then join the two at a single point — typically the exposed thermal pad under the IC, which is itself poured to the PGND pins. The TPS62130A’s datasheet makes that pour mandatory; skipping it shows up as poor regulation or even wrong logic thresholds, because the two grounds shift relative to each other during operation.

The quiet-side components do not get their own vias into the system ground plane — that would couple plane noise straight into the nets that must not see it. They route back to AGND and cross to the power ground only at the single point.

The third dimension: planes and the return path

Everything above is drawn in two dimensions, but the cheapest loop-area reduction on a multilayer board is vertical. AN-1149 recommends a ground plane on both sides of the board, and for boards with more than two layers, a ground plane separating the power plane from the signal plane. Put an unbroken ground plane on the layer directly beneath the power stage and the hot loop’s return closes through the plane, across one thin dielectric: the enclosed area becomes the loop length times the layer spacing, which is smaller than any same-layer return you can draw.

The same plane earns its keep twice more: AN-1149 credits it with reducing ground-loop error and with absorbing EMI radiated by the inductor — which is what makes the “feedback on the opposite side” routing from step 4 work. The grounds of the IC, the input and output capacitors and the diode all connect close together, directly into the plane.

How wide, and how many vias

The numbers, for completeness, both from AN-1149’s traces-and-ground-plane section: power traces as short, direct and thick as possible, with an absolute minimum of 15 mils (0.381 mm) of width per ampere on a standard board; and one standard via per 200 mA wherever significant current must change layers. The 15 mil/A figure is a floor, not a target — the trace width calculator computes the IPC-2221 width for an actual current and an acceptable temperature rise, which comes out wider than the floor for any trace carrying real converter current.

The component note from the same document: prefer a closed-core, low-EMI inductor — toroids and encased E cores are the examples given — because open cores fling their field at everything nearby, and stick cores, in AN-1149’s words, usually emit the most unwanted noise. A closed core makes step 4’s routing problem smaller before any routing happens.

The walk

The five steps, on one board, in the order that protects the thing each step cares about:

1. Input capacitor — against PVIN/PGND, planes not traces, before anything else routes through its path. This is the hot loop; nothing else on the board recovers what this placement loses.
2. Inductor and snubber — close to the IC, SW copper at the minimum that carries the current, inductor rotated to suit.
3. Output capacitor and sense — closes the power path on one layer, no vias; the sense trace routed before lesser signals.
4. Small signal — divider and soft-start at the IC, FB node small, the trace far from the inductor or behind a ground plane.
5. Single-point ground and system vias — power ground and quiet ground joined at the exposed pad; vias outside the circuit, one per amp or better.

The order is the argument: each step spends the board’s remaining freedom on the most expensive remaining mistake. By the time the enable pull-up is placed, there is nothing left for it to ruin — which is exactly how a layout should end.

Sources

• TI SLYT614 — Five steps to a great PCB layout for a step-down converter — the five-step procedure, the input-capacitor priority, the SW-node parasitic-plate model, via placement, and the single-point ground; the 12 V → 3.3 V TPS62130A example circuit.
• TI SNVA021 — AN-1149 Layout Guidelines for Switching Power Supplies — the two-state loop-direction rule, feedback routing, ground planes, the 15 mil/A trace floor, the via-per-200 mA plane transition figure, and inductor core selection.

Updates

• 2026-09-13 — Corrected the special-considerations note on WCSP parts: SLYT614’s preferred fix for a SW pin trapped behind the input capacitor is a thin, short SW trace routed under the capacitor; vias to the inductor are its fallback, and its example is the TPS62360, not the 2.2 µH TPS62130A circuit the earlier wording implied.
• 2026-09-13 — Fig 11 redrawn with the input capacitor against the FETs and the inductor on the SW side, matching the placement rule in Figs 6, 7 and 12; the earlier drawing put the inductor inside the hot loop.
• 2026-09-13 — Fig 10 redrawn: the hot-loop return in the power ground is a one-way path from the PGND terminal to the input capacitor, not a current circulating inside the plane.
• 2026-09-13 — Fig 9 now connects the FB pin to the divider midpoint; Fig 7 given copper under its vias; Fig 2 hops the idle Q2 branch; the input-current wording in Fig 5 and the text made precise.