How a flyback converter works: stored energy and the clamp

Energy goes into the transformer's gap while the switch is on and out through the secondary when it turns off. CCM against DCM, and the leakage clamp.

The flyback is the isolated converter that fits in the smallest box, and the reason is that its transformer is not a transformer. TI’s seminar on the topology says it in its first slide: “energy is stored in flyback transformer” while the switch is on, and only when the switch turns off is the “stored energy transferred to output”. No current flows in both windings at once. The part is an inductor with a gap, wound with a second winding that takes the energy out at a different voltage — a coupled inductor, which is why it needs a gap, why its current waveforms look like an inductor’s, and why the turns ratio does several jobs at once. This article follows SLUP254’s account of the topology and TI’s SNVA866 design procedure for a 20 W supply; the flyback transformer calculator runs that procedure for any specification.

The two states

Two schematics of a flyback converter. Left, switch on: the input drives current through the primary winding and the MOSFET to ground, the rectifier diode is reverse-biased and the output capacitor supplies the load. Right, switch off: the primary current stops, the secondary winding drives current through the diode into the output capacitor and load, and the primary sees the reflected output voltage added to the input on the MOSFET drain. — Fig 1 — The two states. Switch on: the input is across the primary, the current ramps up at V_in/L_M, the dot-marked secondary is reverse-biased, and the output capacitor carries the load — SLUP254: "energy is stored in flyback transformer". Switch off: the winding voltages reverse, the secondary conducts through the rectifier and "stored energy [is] transferred to output", and the output appears on the primary multiplied by the turns ratio, V_OR = (N_P/N_S)·V_out = 10 V here, on top of the input at the drain.

Switch on: the input voltage is across the primary and the current ramps up at V_in/L_M, storing ½·L·I² in the core’s gap. The secondary’s dot is negative, the rectifier is off, and the output capacitor supplies the load alone. Switch off: the magnetising current cannot stop, so the winding voltages reverse until something conducts — the rectifier — and the stored energy flows into the output. While it does, the output voltage appears on the primary through the turns ratio, and the drain sits at the input plus that reflected voltage. SLUP254’s slide adds the two things a real part does in the same instant: “during commutation: leakage energy absorbed by clamp circuit”, and “if DCM operation, all the stored energy is transferred”.

What the turns ratio decides

Because the two windings take turns, the volt-seconds balance across the on-time and the off-time sets the duty cycle. SNVA866 writes it as D = (N_P/N_S·V_LOAD) / (V_SUPPLY + N_P/N_S·V_LOAD), and its design starts there: “the maximum duty cycle occurs when the supply voltage is at the minimum value. By selecting the maximum duty cycle, the number of turns on the secondary winding is calculated.” Its example is an 18–36 V input making 5 V at 4 A with a 10 V bias winding, 20.2 W at 250 kHz. A 40 % target at 18 V asks for 0.417 secondary turns per primary turn; the note rounds to 0.5 — “2 on the primary winding and 1 turn on the secondary” — and the duty cycle at 18 V becomes 35.7 %, at 36 V 21.7 %. Below 50 % matters twice: it “reduces the need for slope compensation which is required for stable operation when the duty cycle is greater than 50 % in CCM operation”, and “the right-half plane zero of the modulator is pushed to high frequencies”.

The same ratio sets two voltage stresses in opposite directions. During the off-time the output reflects onto the primary as V_OR = (N_P/N_S)·V_LOAD — 10 V in the example — and the MOSFET drain sees the input plus it, 46 V at 36 V in, before the leakage spike. During the on-time the input reflects onto the secondary as V_in·N_S/N_P, and the rectifier blocks the output plus it: 23 V. Fewer secondary turns would ease the diode and load the switch; more would do the reverse. The ratio is a division of the total stress between the two semiconductors, and a 100 V MOSFET with a 40 V Schottky is where this example lands.

Inductance, ripple and the peak

The primary inductance sets how much the current ramps in one on-time. SNVA866 weighs three things: “primary winding current ripple ratio, falling slope of the transformer current and the right half plane zero frequency”. More ripple means a smaller inductance and “the core losses increase and the copper losses decrease”; less means a larger part and a lower right-half-plane zero. Its balance: “a maximum ripple ratio between 30 % and 70 % results in a good balance of the total power loss of the transformer”; it takes 60 %, at maximum input where the ripple is largest, and its equation 6 gives 20.6 µH, rounded to 21 µH.

The peak current is then at minimum input: the pedestal P_OUT/(V_{SUPPLY_min}·D) plus half the ripple. For the example, 18 V × 0.357 / (21 µH × 250 kHz) = 1.22 A of ripple on a 3.14 A pedestal, 3.75 A peak — “used to properly size the current sense resistor”, and the transformer’s saturation rating, which the note’s part sets at 6 A. The margin is not generosity: leakage inductance causes “higher duty cycle and magnetizing current than expected”, and the current limit has to sit above the peak with room for both.

Continuous or discontinuous

Two panels of primary and secondary current against time over two switching periods. Left, full load, continuous conduction: the primary ramps from about 2.5 to 3.75 amps during the on-time, the secondary starts near 7.5 amps and ramps down to about 5 amps by the end of the period, and the next primary pulse starts from the pedestal. Right, a tenth of the load: the primary starts from zero each cycle, the secondary ramps to zero before the period ends, and there is an idle gap with no current. — Fig 2 — SNVA866's converter at 18 V, 2:1, 21 µH and 250 kHz. Left, full load: continuous conduction, the primary ramping 1.22 A on a 2.53 A pedestal to 3.75 A, the secondary carrying the same ampere-turns, 7.5 A down to 5.1 A. SLUP254's CCM: "small ripple and rms current", "lower MOSFET conduction and turn-off loss", but a right-half-plane zero because "energy is delivered during 1 − D". Right, a tenth of the load: the secondary reaches zero before the period ends and the converter is in DCM — "all the stored energy is transferred", "no diode reverse recovery loss", "first-order system, inherently stable, no RHPZ problem".

At full load the secondary current is still flowing when the next on-time starts: continuous conduction, and the primary starts each cycle from a pedestal. SLUP254’s case for it: “small ripple and rms current”, “lower MOSFET conduction and turn-off loss”, “lower core loss”, “lower capacitors loss”, “smaller EMI and output filters”, “can have better ‘full load’ efficiency”. Its cost is dynamic. In CCM “energy is delivered during 1 − D”, so a command to deliver more first lengthens the on-time and shortens the delivery — “initial reaction is in opposite direction of desired correction” — which is a right-half-plane zero whose “phase decreases with increasing gain”, and the loop must cross over below it.

Reduce the load and the secondary current reaches zero before the period ends; the converter is in discontinuous conduction, with an idle gap in which nothing conducts and the drain rings down to the input. SLUP254’s case for DCM: “all the stored energy is transferred”, “no diode reverse recovery loss”, “lower inductance value — may result in a smaller transformer”, “better ‘no load’ efficiency”, and above all “first-order system — inherently stable, no RHPZ problem”, so “slope compensation not needed”. The same converter passes between the two as the load changes, and SNVA866’s design is a CCM design at full load that will run discontinuous at light load; the compensation has to survive both.

The leakage, and why there is a clamp

Not all of the primary’s flux links the secondary. SLUP254 models the rest as a leakage inductance in series with the winding, and it is the reason the ideal picture above needs a fourth component. “When FET turns OFF, L_leak2 opposes to I_P decrease and I_S increase”: the leakage’s current has nowhere to go, the drain flies upward, and without a clamp it would keep going until the MOSFET avalanched. The RCD clamp catches it — “during commutation primary-to-secondary, the leakage energy is absorbed by the clamp circuit”, “R_clamp dissipates the leakage energy and some magnetizing energy”, “the clamp capacitor ensures a low voltage ripple” — at a level that is a design choice: “V_clamp is maximum at full load and minimum input voltage”, “R_clamp selected for a maximum drain voltage in worst case”, and the value is a “tradeoff between efficiency, peak drain voltage, output current limit and cross regulation”. A low clamp voltage is safe for the MOSFET and wasteful, because the clamp then also absorbs magnetising energy; a high one is efficient and demands a higher-voltage switch.

Drain voltage against time over one switching period. Near zero during the on-time; at turn-off it spikes to the clamp level above the input plus reflected voltage, rings briefly, then settles at the input plus the reflected voltage for the rest of the off-time. — Fig 3 — The drain during one period, for the example's 18 V input and 10 V reflected voltage with a clamp 15 V above them. At turn-off the leakage inductance "opposes to I_P decrease and I_S increase", the drain flies up until the clamp diode conducts — SLUP254's "voltage spike on FET during commutation", V_in + V_clamp — then "leakage inductance resonates with drain capacitance" and the drain settles at V_in + V_OR while the secondary conducts. The clamp "dissipates the leakage energy and some magnetizing energy"; its voltage is a "tradeoff between efficiency, peak drain voltage, output current limit and cross regulation".

Leakage costs more than the clamp’s watts. SLUP254’s list: “clamp circuits and snubbers needed for primary FET and secondary rectifier(s)”, “lower power-supply efficiency”, “higher duty cycle and magnetizing current than expected”, “higher H-field radiated emission”, “high impact on cross-regulation”, and a commutation that “is not instantaneous and depends on V_clamp” with a “loss of volt-seconds”. The remedy is in the winding, not the circuit: leakage “is a function of winding geometry, number of turns and separation between primary and secondary” — “minimize the separation between the primary and main secondary winding(s)”, “interleave the primary and main secondary”, “select a core with a long and narrow window” — and two things that do not help: leakage “is not lowered with a high permeability core”, and “having the winding tightly coupled to the core will not reduce it”. After the clamp diode recovers, “leakage inductance resonates with drain capacitance”, which is the ringing an RC snubber on the drain damps; the snubber calculator sizes it from the ring.

The worked design, end to end

SNVA866’s example, in the order the note does it:

Turns. 40 % target at 18 V → 0.417 secondary turns per primary turn → chosen 0.5 (2:1) → D_max 35.7 %; bias winding 0.5 × 10 V / 5 V = 1 turn.
Inductance. 60 % ripple at 36 V → 20.6 µH → chosen 21 µH.
Currents. At 18 V: 1.22 A of ripple, 3.75 A peak; secondary peak 7.5 A. Transformer saturation rating 6 A.
Stresses. V_OR = 10 V; drain 46 V at 36 V in plus the clamp spike; rectifier 23 V.
Clamp. Chosen from the leakage of the transformer actually wound, against the MOSFET rating and the efficiency target.

Every number above 21 µH is in the calculator; the leakage is in the transformer.

Sources

TI, SLUP254 — Under the Hood of Flyback SMPS Designs, 2010 Power Supply Design Seminar. Energy transfer, CCM against DCM, the right-half-plane zero, the RCD clamp, leakage inductance and its effects, winding geometry, cross-regulation.
TI, SNVA866A — How to Design an Isolated Flyback Using the LM5155, 2023. The CCM design procedure and its 18–36 V, 5 V / 4 A, 250 kHz example: equations 2–8 and the chosen transformer.