Why an LDO oscillates: the output capacitor's ESR tunnel

The ESR zero that keeps a PMOS LDO stable, the tunnel where too little and too much both oscillate, why ceramics broke old parts, and what C_NR and C_FF trade.

An LDO that oscillates or measures noisy almost always has the right voltage and the wrong output capacitor — and “wrong” is decided by one line in the data sheet. If the part is an older PMOS or PNP design, its output capacitor’s ESR must sit inside a stated window — 0.1 Ω to 20 Ω in TI’s worked example: below the window the loop oscillates, and above it the loop oscillates too. If the part is a modern “ceramic-stable” design, the window is gone and a plain ceramic is exactly what it wants. Fitting a low-ESR ceramic to the former, or assuming the latter without reading the data sheet, is the whole failure mode.

Noise is the same story seen from the other side. The hiss on an LDO output comes from its bandgap reference, scaled by V_OUT/V_BG, and the two capacitors that tame it — the noise-reduction capacitor on the reference and the feed-forward capacitor across the top feedback resistor — both charge slowly enough to show up in the startup time. Everything below is the working behind those two rules, from TI’s stability note SLVA115, their noise articles SLYT201 and SSZTA13, and Würth’s measured capacitor impedance spectra in ANP109.

The three poles a PMOS LDO has to survive

SLVA115 opens with the anatomy. A PMOS or PNP pass-element LDO has three poles that matter: the dominant pole P(DOM) set inside the error amplifier, the load pole P(LOAD) formed by the output capacitor and the load — so it moves with load current — and the pass-device pole P(PASS) formed by the parasitic capacitance of the big pass transistor. Each pole contributes 90° of phase shift and another −20 dB/decade of gain slope, and a three-pole, high-gain loop does not survive that without help. The note’s stability condition is the classic one: the regulator is unconditionally stable if the open-loop gain rolls off at −20 dB/decade — like a single-pole system — when it crosses 0 dB.

A PMOS LDO regulator loop: the error amplifier compares the divided output against the bandgap reference and drives the PMOS pass element. The output capacitor is drawn as its capacitance in series with its ESR, and it is this resistance inside the feedback path that creates the compensating zero. — Fig 1 — The loop SLVA115 analyses. The output capacitor is never a pure capacitance: its ESR is in series, inside the loop, and the zero it forms with C_OUT is the cheapest compensation the regulator can get — which is why the data sheet of an older PMOS LDO specifies the ESR, not just the capacitance.

The standard cure for a pole is a zero, and an LDO already carries the component to make one. The output capacitor is required for normal operation anyway, and no real capacitor is pure: its equivalent series resistance sits in series with the capacitance, inside the feedback loop. SLVA115 calls using it “typically the simplest and least expensive method for generating this zero”.

The zero the output capacitor donates

The zero lands at

$f_{Z(ESR)} = \frac{1}{2\pi \, R_{ESR} \, C_{OUT}}$

and its job is to cancel the phase shift and slope of one of the three poles before the gain reaches 0 dB. Fig 2 computes the open-loop response from exactly this model — three poles and the ESR zero between the load pole and the pass pole — and shows the shape SLVA115 draws: the slope steepens to −40 dB/decade after P(LOAD), the zero pulls it back to −20 dB/decade, and the curve crosses 0 dB at a single-pole slope with P(PASS) still safely above.

Open-loop gain of a PMOS LDO falling from 90 dB across frequency: the dominant pole starts a 20 dB per decade roll-off, the load pole steepens it to 40 dB per decade, the ESR zero returns it to 20 dB per decade so the curve crosses 0 dB at a single-pole slope before the pass-device pole arrives. — Fig 2 — The open-loop response SLVA115 draws for a PMOS or PNP LDO, computed here from a three-pole-one-zero model (poles at 100 Hz, 10 kHz, 500 kHz, zero at 100 kHz). The ESR zero cancels one pole so the gain crosses 0 dB at −20 dB/decade — the condition the note gives for unconditional stability.

Both halves of that sentence carry a constraint, and SLVA115 states them as a pair:

The ESR must be high enough to lower the fZ(ESR) frequency so that the gain slope is –20 dB/decade instead of –40 dB/decade (–2) when it crosses 0 dB, but low enough so that the fZ(ESR) frequency is high enough for the gain to be below 0 dB before P(PASS).

Too little ESR and the zero sits far above crossover, useless — the gain crosses 0 dB at −40 dB/decade with two poles’ worth of phase shift. Too much ESR and the zero arrives so early that it flattens the roll-off and props the gain up past P(PASS), where the crossing is steep again. Fig 3 runs the same loop with three ESR values on a 2.2 µF capacitor and computes the crossover and phase margin for each: 1 Ω is stable, 5 mΩ of ceramic ESR oscillates, and 20 Ω is back to marginal.

Three loop-gain curves for the same LDO with different output capacitor ESR. With 1 ohm the zero lands before crossover and the gain crosses 0 dB at a single-pole slope with healthy phase margin. With 5 milliohms of ceramic ESR the zero sits beyond 14 MHz, the gain crosses at 40 dB per decade and the phase margin is gone. With 20 ohms the zero comes so early that the gain stays high until after the pass pole and the crossing is steep again. — Fig 3 — One loop, three ESR values, C_OUT = 2.2 µF. The zero frequency 1/(2π·R·C) is computed for each: 1 Ω lands it before crossover (stable); 5 mΩ of ceramic pushes it past 14 MHz, out of reach (unstable); 20 Ω drags it so low the gain shelf persists past P(PASS) (marginal). Both ends of the ESR range fail — the tunnel of Fig 4.

The tunnel: the data sheet draws a window, not a minimum

Older TI regulator data sheets publish this directly as an ESR-versus-load graph with a region of stability in the middle — a tunnel. For the TPS76050 with its minimum 2.2 µF of output capacitance, SLVA115 reads the curve as: the ESR must be between 0.1 Ω and 20 Ω. The note adds two practical glosses. First, “few capacitors have more than 2 Ω of ESR, so the upper limit on the ESR can usually be ignored” — the ceiling exists but rarely binds. Second, the ESR plotted is the capacitor’s minimum ESR, because ESR varies over frequency. Stated as a product, an ESR-times-capacitance larger than 2.2 × 10⁻⁷ ΩF but less than 4.4 × 10⁻⁵ ΩF keeps the TPS760 stable, as long as the capacitance itself stays above the minimum.

The region of stability for an older PMOS LDO drawn as a horizontal band between 0.1 ohm and 20 ohms of ESR across the load current range. The minimum ESR measured at self-resonance for an MLCC, a film capacitor and a low-ESR aluminium electrolytic all sit below the floor of the band, in the region of instability. A dashed line marks the same electrolytic at its 120 hertz data-sheet ESR, which sits inside the band but is not the minimum the tunnel is drawn for. — Fig 4 — The tunnel: SLVA115's region of stability for the TPS76050 with its minimum 2.2 µF, between 0.1 Ω and 20 Ω of ESR. SLVA115 draws it for the capacitor's minimum ESR, so the solid lines are the ESR ANP109 measured at self-resonance — the value the note calls most trustworthy — for a ceramic, a film part and a low-ESR aluminium electrolytic. All three fall through the floor. The dashed line is the same electrolytic's 0.14 Ω at 120 Hz, the figure a data sheet quotes: inside the tunnel, but not the number the tunnel is drawn for.

Note what the capacitance term in f_Z(ESR) means for the floor of the tunnel: it is the capacitance the part actually delivers in circuit, and a class 2 ceramic loses a large fraction of its rated capacitance under DC bias. A capacitor picked to sit just inside a stability window at zero volts can drift toward the window’s edge at the working rail voltage — one more reason windows this narrow age badly.

The ESR your capacitor technology hands you

The tunnel would be harmless if every capacitor technology offered a few hundred milliohms. They do not, and the honest way to see it is Würth’s ANP109 — the same application note that anchored the capacitor half of the ferrite-bead article. It models every capacitor, MLCC to supercapacitor, as one series circuit: the pure capacitance C_S, the equivalent series resistance R_ESR, and the equivalent series inductance L_ESL. Two characteristic frequencies locate everything on the impedance curve:

$f_{RC} = \frac{1}{2\pi \, R_{ESR} \, C_S} \qquad\qquad f_{LC} = \frac{1}{2\pi \sqrt{L_{ESL} \, C_S}}$

and the note’s description of f_LC is the one-sentence version of every impedance plot on this site:

Below this frequency the capacitor acts as capacitor, i.e. can be charged. Above this frequency, the capacitor acts as inductor.

That is the same self-resonance that decides why 100 nF stops working where it does, and the same series model the decoupling calculator plots. What matters here is the floor of the V: at self-resonance the reactances cancel and the impedance minimum is the ESR.

Impedance magnitude against frequency for three measured capacitors, each a V-shaped curve: capacitive and falling on the left, a minimum equal to the ESR at self-resonance, inductive and rising on the right. The aluminium electrolytic resonates lowest, the film capacitor in the megahertz, the MLCC in the tens of megahertz, and all three floors sit near or below a tenth of an ohm. — Fig 5 — |Z| computed from ANP109's series C_S–R_ESR–L_ESL model, using the values the note measured: 265 µF electrolytic (f_LC = 68.5 kHz, 0.04 Ω), 495 nF film (1.94 MHz, 0.04 Ω), 23 nF MLCC (45.8 MHz, 0.06 Ω); each L_ESL is recovered from the measured resonance. The floor of the V is the ESR — and for every modern technology it is well under the 0.1 Ω an old LDO needs.

ANP109’s measured values put numbers on the technologies. A 270 µF aluminium electrolytic measures 265 µF, with 0.14 Ω of ESR at the 120 Hz where electrolytic data sheets quote it, falling to 0.04 Ω at its 68.5 kHz self-resonance. The note is careful about which of those two numbers to trust. Its measured ESR does climb toward low frequencies, but below about 1 kHz that climb “is, however, probably not due to any real physical effect, it is a measurement artefact” — an LCR meter cannot separate the real and imaginary parts of an impedance whose loss angle is near zero — and so “the values around or at f_LC are most trustworthy”, while the 120 Hz figures are listed “for the sake of completeness” with the warning that they “may contain a large error”. A 470 nF film capacitor resonates at 1.94 MHz with about 0.04 Ω. A 22 nF MLCC resonates at 45.8 MHz with about 0.06 Ω, and the note calls even that a conservative estimate: “the actual ESR might be even lower.” (The supercapacitor in the same note bottoms out at 0.007 Ω, for completeness.)

Lay those floors over the tunnel, as Fig 4 does, and the history of LDO stability problems becomes a geometry exercise — with one trap in it. Read at its 120 Hz data-sheet figure, the electrolytic appears to sit inside the window. Read at its minimum, which is the value SLVA115 says the tunnel is drawn for, it is at 0.04 Ω: below the floor, in the same region of instability as the ceramic and the film part. A low-ESR aluminium electrolytic is not a passport into the tunnel. What the window asks for is a capacitor whose ESR stays above 0.1 Ω all the way through self-resonance — a question for that part’s impedance curve, not for the one number printed on its data sheet.

Why the ceramic killed the old designs

SLVA115 is explicit that the tunnel was drawn for a different era: the TPS760 “was designed when tantalum capacitors were common and 1.1 mA was considered low IQ.” A tantalum or general-purpose aluminium electrolytic of that era carried enough ESR by construction to land inside the window — the zero arrived in the right decade without anyone thinking about it. Then MLCCs became cheap, dense and tiny, and every schematic replacement of “2.2 µF electrolytic” with “2.2 µF ceramic” silently moved f_Z(ESR) up by two to three orders of magnitude, out past P(PASS) where it compensates nothing.

The application note demonstrates the failure on hardware: a TPS76050 with a 2.2 µF ceramic rings continuously after a load step — the note reads it as instability, not settling — and the same regulator with the same ceramic plus a deliberate 1 Ω series resistor is cleanly stable. One ohm of resistance, put back on purpose, is the entire difference between an oscillator and a regulator.

If a legacy PMOS LDO must live with a ceramic, that is the shape of the fix: either a small series resistor to rebuild the zero, or a capacitor technology that carries its own — and when the bill of materials says only 225 or 107 on a chip part, the capacitor code tool will at least confirm what value is actually fitted before the ESR question even starts.

“Ceramic-stable” is a redesign, not a marketing line

Newer LDOs invert the requirement. SLVA115’s comparison device, the TPS7A25, is “stable with a minimum of 1.0-µF ceramic capacitor with no additional ESR”, and for parts like it “there is no need to be concerned about ESR unless you wish to use very large capacitors for hold up.” The TPS7A26 goes further and stays stable with 100 µF on its output. The note’s conclusion draws the line plainly: ESR is very important with older regulators, while newer devices are “inherently ceramic capacitor stable”.

The difference is internal compensation — the zero the electrolytic used to donate is now designed into the IC, so the loop crosses 0 dB at a single-pole slope with a nearly ideal capacitor outside. That is why “ceramic-stable” genuinely partitions the LDO world, and why the fix for an oscillating legacy design is never to hope, but either to add the series resistance the loop expects or to move to a part whose data sheet says the words.

The test that settles it: step the load and count the rings

Whichever side of the line the part is on, SLVA115 gives one empirical verdict: “performing a load transient test and observing the amount of ringing on the output is the best way to determine if the capacitor selected is stable.” The recommended setup is a MOSFET switch driven by a function generator — faster than most electronic loads — with the output AC-coupled on a scope. And the pass criterion is refreshingly blunt:

Typically, four rings or less indicate sufficient phase margin for the device to be stable.

Two AC-coupled output voltage traces after the same load current step. The marginal capacitor produces a long train of rings that decays slowly, indicating too little phase margin. The stable case dips once and settles within a few rings, which is the pass criterion of four rings or less. — Fig 6 — SLVA115's verdict test: step the load with a fast MOSFET switch and count the rings. Both traces are the same second-order model with only the damping changed. Four rings or less indicates sufficient phase margin; the top trace is what a 2.2 µF ceramic did on the TPS76050 — oscillation, not just ringing.

The ring count is phase margin made visible. A loop with healthy margin dips once and settles; a loop near the edge rings on and on at its crossover frequency. The same test, run across the load range and at temperature, is what the tunnel plot compresses into one curve.

Noise is not PSRR, and it starts in the bandgap

The second half of the problem is noise, and SLYT201 begins by splitting a conflation that survives on lab benches everywhere:

PSRR refers to the amount of ripple on the output coming from ripple on the input. Noise, on the other hand, is purely a physical phenomenon that occurs with transistors and resistors (capacitors are noise-free) on a very fundamental level.

Noise is specified two ways: spectral density in µV/√Hz against frequency, and that density integrated over a band as a single µVrms number. Every internal source is referred to the error-amplifier input and then amplified to the output by the closed-loop gain,

$A_{CL(DC)} = \frac{V_{OUT}}{V_{BG}}$

where V_BG is the internal bandgap reference, about 1.2 V in most parts. The scaling is worth internalising: a 3.0 V LDO has almost twice the output noise voltage of a 1.5 V one, from identical internals — comparing noise numbers across different output voltages without correcting for the ratio is comparing nothing.

The LDO block diagram with its noise sources marked: the bandgap reference feeding through an internal resistor and external noise-reduction capacitor, the feedback divider contributing thermal noise, and the error amplifier input stage. The large pass FET is marked as not a primary contributor because its noise is divided by the loop gain when referred to the input. — Fig 7 — SLYT201's map of LDO noise. Everything that touches the error-amplifier input — bandgap, divider, input stage — reaches the output multiplied by V_OUT/V_BG. The pass FET, half the die, barely matters: its noise is divided by the open-loop gain on the way back to the input. The one external lever on the dominant source is C_NR.

Three sources sit at that input and therefore matter: the bandgap — usually dominant — the feedback divider, whose thermal noise goes as 4kTR of R1 ∥ R2 (smaller resistors are quieter, at the price of divider current), and the amplifier’s own input stage, which nothing external can touch. The counter-intuitive absence is the pass FET: half the die, and negligible, because its noise is divided by the open-loop gain on the way back to the input.

The noise-reduction capacitor buys silence with startup time

The one external lever on the dominant source is the noise-reduction pin. Internally a large resistor, externally a capacitor C_NR, together a low-pass filter on the bandgap output — SLYT201 puts its cutoff “somewhere between 1 and 500 Hz, therefore filtering out nearly all of the noise coming from the bandgap”. The same filter, not coincidentally, is also used to improve PSRR.

The price is startup. The filtered reference has to charge through that large internal resistor, and “the time to charge the filtered bandgap increases drastically” with capacitance. This is why fast-charge circuits exist: SLYT201 cites the TPS793/4/5/6xx and TPS799xx families starting in 50 to 100 µs even with a fairly large 0.01 µF noise-reduction capacitor. And the payoff curve flattens — there is, in the note’s words, a point where increasing this capacitance offers no further improvement, because the divider and amplifier noise remain underneath.

Two curves against noise-reduction capacitance on a log axis: the output noise falls as the bandgap filter cutoff drops, then flattens onto the floor set by the divider and amplifier noise, while the startup time rises in direct proportion to the capacitance. The useful region is where the noise curve has fallen but not yet flattened. — Fig 8 — The C_NR trade-off, from a first-order model of SLYT201's description: the internal resistor and C_NR form a low-pass filter (cutoff somewhere between 1 and 500 Hz) that strips the bandgap noise, but the same RC must charge before the output can start. Past the point where the divider and amp noise floor takes over, more capacitance buys only startup delay — which is why fast-charge circuits exist: with 0.01 µF, a TPS793–796 still starts in 50 to 100 µs. The noise curve is on a linear relative scale and the startup-time curve on a logarithmic one (a straight line because time is proportional to C_NR); the two have no common axis, so where they cross means nothing.

Stability and noise are the same problem

SLYT201’s most useful observation is that the two halves of this article are one subject. The closed-loop gain is not flat at V_OUT/V_BG forever; near the unity-gain frequency, a loop with low phase margin peaks, and the peak multiplies the noise passing through it. High load current and low output capacitance both erode phase margin, so both raise output noise — and then the note closes the loop back to the first half:

many times a higher equivalent series resistance (ESR) capacitor will actually reduce noise. This is because a larger ESR creates a lower-frequency zero, which many times may improve the LDO stability.

Spectral noise density against frequency on log axes: a 1-over-f region falling toward a flat thermal region, then rolling off above the loop bandwidth. A second curve with low phase margin is identical until near the unity-gain frequency, where closed-loop peaking lifts the noise into a hump before the roll-off. — Fig 9 — A spectral noise density in the shape SLYT201 plots (µV/√Hz from 10 Hz to 100 kHz), computed from a flicker-plus-thermal source shaped by the closed-loop response. Same sources, two phase margins: the loop with low phase margin peaks near its unity-gain frequency and amplifies its own noise there — stability and noise are one problem, not two.

A noise hump near the loop bandwidth in a spectral density plot is not a noise problem; it is a phase-margin problem wearing a noise costume. Fixing the output capacitor fixes both readings.

The feed-forward capacitor: a zero you place yourself

SSZTA13 adds the second external lever, available only on adjustable LDOs because it lives in the external divider: a feed-forward capacitor C_FF in parallel with the top feedback resistor. At DC the divider still sets

$V_{OUT} = V_{REF}\left(1 + \frac{R_1}{R_2}\right)$

but within the error amplifier’s bandwidth the AC content of the reference — its noise — is amplified by the same factor. C_FF is an AC shunt across R1: for the band it shorts, the noise gain falls toward unity while the DC set point stays put.

An adjustable LDO output stage with the feed-forward capacitor drawn in parallel with the top feedback resistor. The capacitor and R1 form a zero, and the capacitor with the parallel combination of both resistors forms a pole at a higher frequency. — Fig 10 — The feed-forward capacitor, exactly where SSZTA13 puts it: in parallel with the top resistor of the divider. It only exists on adjustable LDOs, because the divider must be external. At high frequency it shorts R1, so the AC gain from the reference falls toward unity — the noise between Z_FF and P_FF is no longer multiplied by 1 + R1/R2.

The effect on the numbers is concrete: on the TPS7A91, adding 100 nF across the top resistor cuts integrated noise from 9 µVrms to 4.9 µVrms. The two capacitors also divide the spectrum between them — SSZTA13’s rule-of-thumb table credits C_NR mostly below 1 kHz and C_FF mostly in the 1 kHz to 100 kHz band, with some help on either side.

In the loop, C_FF introduces a zero and a pole:

$Z_{FF} = \frac{1}{2\pi \, R_1 \, C_{FF}} \qquad\qquad P_{FF} = \frac{1}{2\pi \, (R_1 \parallel R_2) \, C_{FF}}$

The zero always comes first, because R1 is larger than R1 ∥ R2. Placed before the unity-gain frequency, it improves phase margin; in SSZTA13’s example the crossover moves from about 200 kHz to about 300 kHz and the phase comes up with it, while P_FF lands beyond the crossover where its effect on phase margin is minimal. Fig 11 computes the same manoeuvre on a two-pole loop, and the improved margin shows up in hardware as a load transient that rings less and settles quicker.

Loop gain and phase with and without the feed-forward capacitor. Without it the gain crosses unity earlier with little phase margin. The feed-forward zero lifts the gain slightly, moving the crossover higher in frequency, but lifts the phase much more, so the phase margin at the new crossover is several times larger. — Fig 11 — A two-pole loop with and without a feed-forward zero, computed. The zero moves the unity-gain crossing out slightly — SSZTA13's example moves from about 200 kHz to about 300 kHz — and buys back phase exactly where the loop needs it. P_FF sits above the crossover, so its cost lands where the loop no longer cares.

What C_FF does to PSRR — and what it costs at startup

Loop gain is rejection. By lessening the gain roll-off in the band between its zero and pole, C_FF improves the loop response there, and SSZTA13’s PSRR curves for the TPS7A8300 show the corresponding lift; increasing the capacitance pushes the zero — and the improvement — to lower frequencies.

Power-supply rejection against frequency for no feed-forward capacitor and two increasing values. Rejection is high at low frequency and falls as loop gain falls; each feed-forward zero holds the rejection up longer through the middle decades, and the larger capacitance moves that improvement down to lower frequencies. Without the capacitor the low-phase-margin loop dips below zero decibels near its crossover, where input ripple is amplified rather than rejected. — Fig 12 — PSRR modelled as the loop gain's doing (rejection ≈ 20·log|1 + T|), for the loop of Fig 11. The feed-forward zero lessens the gain roll-off, and the loop response it buys in that band is PSRR in the same band. Increasing C_FF pushes the zero — and the improvement — leftward, exactly as SSZTA13 describes on the TPS7A8300. Near crossover the no-C_FF loop, with about 14° of phase margin, drops below 0 dB: |1 + T| is less than one there, so input ripple is amplified — the closed-loop peaking of Fig 9 seen from the supply side. The 10 × C_FF loop dips deeper still, because its P_FF has moved down to 100 kHz and sits at the crossover, cutting the margin to about 13°: the badly placed zero-pole pair the next paragraph warns of, and why a larger C_FF is not free.

The limits are the same as ever. A badly placed zero-pole pair can destabilise the loop, so the data sheet’s C_FF limits bind, and TI’s general recommendation is 10 nF to 100 nF. And the startup cost returns, in a new disguise: SLYT201 already named the mechanism for a capacitor across the top resistor — it “could potentially slow down start-up time significantly, since the capacitor would have to be charged by the current in the resistor divider.” Milliseconds of delay per hundred nanofarads through a 10 kΩ-class divider, as Fig 13 computes.

Output voltage rising toward regulation after enable, for three feed-forward capacitor values. With none the output settles almost immediately; with 10 nanofarads the rise to 90 percent stretches to about 230 microseconds; with 100 nanofarads it takes about 2.3 milliseconds, because the capacitor must charge through the feedback divider. — Fig 13 — Startup computed from an RC charging model: the feedback capacitor has to charge through the divider (here R1 ∥ R2 = 10 kΩ), so the time to regulation stretches with C_FF — the mechanism SLYT201 names for the capacitor across the top resistor. SSZTA13 recommends 10 nF to 100 nF and notes only that a large C_FF brings other challenges; startup is one of them. The marked times are where each curve reaches 90 % of final value.

The checklist

Before the LDO goes on the schematic:

Which side of the line is the part? Read the output-capacitor section of the data sheet. A stated ESR window means a legacy PMOS/PNP design; the words “ceramic capacitor stable” mean the opposite requirement.
For a legacy part, is the ESR inside the tunnel at your load? Use the capacitor’s minimum ESR, at the capacitance the part really delivers under its DC bias — not the rated value.
For a ceramic-stable part, is the ceramic real? Check the value on the fitted part, and stay within any maximum-capacitance note.
Step the load and count the rings. Four or less, across load and temperature.
Noise too high? C_NR for below 1 kHz, C_FF (10–100 nF, adjustable parts only) for the midband — and re-check startup time after fitting either.

Sources

TI SLVA115 — ESR, Stability, and the LDO Regulator — the three-pole loop, the ESR zero, the TPS76050 stability tunnel (0.1–20 Ω at 2.2 µF), the load-transient test and the four-rings criterion, and the ceramic-stable TPS7A25/TPS7A26 comparison.
TI SLYT201 — Understanding noise in linear regulators — noise versus PSRR, the bandgap as dominant source, the V_OUT/V_BG noise gain, the noise-reduction filter (1–500 Hz) and its startup cost, closed-loop peaking, and why higher ESR can reduce noise.
TI SSZTA13 — LDO Basics: Noise — How a Feed-forward Capacitor Improves System Performance — the C_FF placement, the Z_FF/P_FF equations, the 9 → 4.9 µVrms TPS7A91 measurement, the 200 → 300 kHz crossover example, the TPS7A8300 PSRR curves, and the 10–100 nF recommendation.
Würth ANP109 — Impedance Spectra of Different Capacitor Technologies — the series C_S–R_ESR–L_ESL model, the characteristic frequencies, the measured ESR of the electrolytic, film and ceramic parts used in the figures here, and why the values at self-resonance are the ones to trust.

Updates

2026-09-13 — Fig 4 and the paragraph it belongs to corrected: the aluminium electrolytic was plotted at its 120 Hz ESR of 0.14 Ω, inside the tunnel, while the ceramic and film parts were plotted at their self-resonance minima. SLVA115 draws the tunnel for the capacitor’s minimum ESR, and ANP109 measures this part’s minimum at 0.04 Ω — below the floor, with the other two. The claim that its low-frequency ESR rise is “real physics, not an artifact” is withdrawn; ANP109 says the rise below about 1 kHz is a measurement artefact.
2026-09-13 — Fig 7 label under the pass FET corrected: its noise is negligible because it is divided by the large loop gain between it and the error-amplifier input, not because there is no gain there. Footer now reads “almost twice”, as SLYT201 puts it.
2026-09-13 — Fig 6 redrawn so the output dips downward first after the load-current step, as in SLVA115’s scope capture.
2026-09-13 — Fig 12 axis extended to −20 dB: the no-C_FF loop dips below 0 dB near crossover, where input ripple is amplified, and the old axis clipped that away. The same axis shows that the 10 × C_FF case dips too, because its P_FF lands at the crossover and costs the loop its phase margin.
2026-09-13 — Fig 8 now states that its startup-time curve is on a log scale; Fig 13’s caption no longer attributes the 100 nF upper limit to startup time, which SSZTA13 does not say.
2026-09-13 — Fig 3, Fig 5, Fig 11 and Fig 12 redrawn to keep curves off the key text and to make the faint film and no-C_FF curves legible; Fig 13 alt text corrected to the marked 230 µs and 2.3 ms.