Tag
buses
5 articles.
- Level shifters: one MOSFET per line, or a translator IC
A 3.3 V device and a 5 V device can share a line safely. For open-drain buses one MOSFET per line does it, with no direction pin: AN10441's circuit.
- SPI vs I2C: which is faster, and why the answer is both
SPI is faster because nothing caps its clock and it spends 8 clocks per byte; I2C spends 9 and stops at 3.4 Mbit/s. Four reasons the choice is not about speed.
- UART baud rate error: how much you can get away with
Why 2 % per end is the limit, where 8.5 % errors come from, what the odd crystal values buy, and what a fractional baud divider costs you in return.
- I2C pull-up resistors: the value is a window, not a number
Size an I²C pull-up from both ends: Rp(min) from the 3 mA sink limit, Rp(max) from rise time and bus capacitance — with the worked window at 3.3 V, 200 pF.
- RS-485 termination: when 120 Ω helps and when it just costs you
Where the 120 Ω comes from, the loop-time test that decides if you need it, AC termination as a data-rate trade, and how failsafe bias eats your node budget.