Level shifters: one MOSFET per line, or a translator IC

A level shifter is what goes between two devices that speak the same protocol from different supplies. A 3.3 V microcontroller and a 5 V peripheral each expect the line to swing between their own ground and their own rail; without something between them, one of two things goes wrong. TI’s note on selecting a translator names both: the higher-voltage device can damage or mis-bias the lower one unless “the input pins of the receiving device must be specified to be tolerant to the higher voltage”, and the lower-voltage device driving upward “simply does not have enough logic swing to pass through the input V_IH level of the receiving device”. For push-pull signals the answer is a translator IC. For an open-drain bus like I²C the answer can be one transistor per line, and Nexperia’s AN10441 is the two pages that describe it. That circuit’s numbers — how much gate drive it has, what a pulling device has to sink, how long the far side waits — are what the MOSFET level shifter calculator checks. This article is what a level shifter does, how the one-FET version works, and where it stops.

Why a different supply is a problem in both directions

SCEA030 lays the two directions out. High driving low “often can reliably drive lower-voltage logic without special translation circuitry” if the receiver is overvoltage tolerant and the swing crosses its thresholds; the reasons it may not be tolerant are gate-oxide limits, an ESD diode to V_CC that “provides a current path”, or an I/O port with “a parasitic diode to V_CC”. Low driving high has the opposite problem: the swing may never reach V_IH, and even when it does, “the V_IH level may not be sufficiently high to completely turn off the PMOS device in the input buffer”, so the receiver draws static current — the ΔI_CC condition.

Open-drain outputs sidestep the second problem by construction. SCEA040: the output level “depends on V_CCB”, the required input level “depends on V_CCA”, and an open-drain output pulled up to the receiver’s rail produces the receiver’s own high. The cost is the one every pull-up resistor carries — SCEA030’s “two basic disadvantages”: current in the resistor while the line is low, and a low-to-high edge that “is determined by the RC time constant of the resistor and the load, and can be slow”. But it only translates one way: an open-drain output on the low side pulled up to the high rail sees the high rail on its own pin. For a bus where both sides pull, both sides need to be protected, and the direction changes without warning.

The one-MOSFET bidirectional shifter

AN10441’s circuit is a single N-channel MOSFET per bus line: gate to the lower supply, source to the low-voltage bus, drain to the high-voltage bus, and pull-ups on each side to that side’s rail. It has no direction pin and no supply of its own, and the note claims two extras for free: it “isolates a powered-down bus section from the rest of the bus system” and “protects the ‘lower voltage’ side against high voltage spikes from the ‘higher-voltage’ side”. The operation is three states, quoted from the note because the wording is the whole design:

1. No device is pulling down the bus line. The bus line of the ‘lower-voltage’ section is pulled up by its pull-up resistors R_p to 3.3 V. The gate and the source of the MOSFET are both at 3.3 V, so its V_GS is below the threshold voltage and the MOSFET is not conducting. This allows the bus line at the ‘higher-voltage’ section to be pulled up by its pull-up resistor R_p to 5 V.

2. A 3.3 V device pulls down the bus line to a LOW level. The source of the MOSFET also becomes LOW, while the gate stays at 3.3 V. V_GS rises above the threshold and the MOSFET starts to conduct. The bus line of the ‘higher-voltage’ section is then also pulled down to a LOW level by the 3.3 V device via the conducting MOSFET.

3. A 5 V device pulls down the bus line to a LOW level. The drain-substrate diode of the MOSFET [pulls] the ‘lower-voltage’ section down until V_GS passes the threshold and the MOSFET starts to conduct.

— Nexperia, AN10441

“State 1 performs the level shift function. States 2 and 3 perform a ‘wired-AND’ function between the bus lines of both sections as required by the I²C-bus specification.” Supplies “other than 3.3 V for V_DD1 and 5 V for V_DD2 can also be applied, e.g., 2 V for V_DD1 and 10 V for V_DD2 is feasible”, with the one rule that V_DD2 “must be equal to or higher than V_DD1”.

The numbers in the three states

Each state has a condition the note states in words and the design has to meet in volts.

State 2 needs gate drive. With the source at V_OL and the gate at V_DD1, the FET has V_DD1 − V_OL of gate drive — 2.9 V for a 3.3 V side with the I²C 0.4 V low. That must exceed the FET’s threshold with margin, and it is the threshold maximum on the datasheet that counts. For a 1.8 V low side the drive is 1.4 V, and a FET with a 1.5 V maximum threshold never turns on; the part has to be chosen for its threshold, not its on-resistance.

State 3 needs more. The high side pulling low reaches the low side only through the body diode, so the low side first drops to V_OL + V_F, about 1.1 V, and the FET turns on only if V_DD1 exceeds V_OL + V_F + V_GS(th) — 2.6 V for a 1.5 V threshold. A 2.5 V low side with that FET is stuck at a diode drop.

Both states load one driver. Whichever device pulls low sinks its own pull-up and the other side’s through the FET. For 4.7 kΩ to 3.3 V and 4.7 kΩ to 5 V that is 0.62 + 0.98 = 1.60 mA, under the I²C 3 mA; two 2.2 kΩ pull-ups would be 3.4 mA, over it.

The far side’s low is not V_OL. It is V_OL plus the far pull-up’s current through R_DS(on) — at the gate drive actually available, not the headline figure. At 2 Ω and 0.98 mA that is 2 mV and irrelevant; at the tens of ohms a marginal-threshold FET shows with 1.4 V of drive, it is not.

The edge the shifter adds

Pulling low, both sides fall together. Releasing, they do not rise together. The low side rises on its own pull-up and capacitance; the FET stays on until the source has risen to within V_GS(th) of the gate — to V_DD1 − V_GS(th), 1.8 V here — and only then does the high side start up its own RC. That wait is R_p1C₁ ln(V_DD1/V_GS(th)), 371 ns for 4.7 kΩ, 100 pF and a 1.5 V threshold. It is not a rise time and the specification does not have a line for it; it is a delay the timing budget has to absorb, and at 400 kHz it is a third of the clock-low period. A lower threshold shortens it; so does a smaller low-side pull-up.

The rise times themselves are the plain I²C pull-up arithmetic, one side at a time: 0.8473·R·C for the 30–70 % the specification measures, against 1000 ns in Standard-mode and 300 ns in Fast-mode. 4.7 kΩ into 100 pF is 398 ns — a Standard-mode value on either side of the shifter, as it would be without one.

The window is narrower than for one bus, because the sink-current floor is paid by one device for two pull-ups: with equal pull-ups, 3 mA is reached at 2.5 kΩ, and Fast-mode’s rise time at 3.5 kΩ. That is the range, and 3.3 kΩ is in it.

When to use a chip instead

AN10441 is explicit that the circuit “is not intended for Hs-mode systems”, and it is an open-drain device: a push-pull driver on either side simply fights the FET. SCEA030’s catalogue is the map of what to use when the one-FET shifter does not fit. For push-pull signals with no direction pin available, the auto-direction “TXB push-pull buffered type architecture … is designed to exclusively be connected and interfaced with a push-pull CMOS driver”, for SPI and SD; “the TXB010x devices are not intended for use in open-drain applications”. For open-drain buses that need more than a discrete FET gives — defined rise-time acceleration, specified partial-power-down behaviour — “the TXS translators are designed to interface with open-drain drivers and can be used in applications such as I²C”. For signals in one direction with a fast edge, a dual-supply buffer; for translating down by roughly a threshold, a plain FET switch, which the note says “inherently translate only in the downward direction, with a translation difference equal to the threshold voltage of the FET, approximately 1 V”.

The one-FET shifter is for the case in the middle: an open-drain bus, Standard or Fast mode, two supplies with the lower one high enough to drive the FET, and no need for the edges to be better than a pull-up gives. That is most I²C buses on most boards, which is why the circuit is everywhere — and why the numbers above are worth a minute before it goes on the schematic.

Worked numbers

The calculator’s defaults, AN10441’s supplies:

V_DD1 3.3 V, V_DD2 5 V, R_p 4.7 kΩ each side, C 100 pF each side
FET: V_GS(th) 1.5 V max, R_DS(on) 2 Ω at 2.9 V drive, V_F 0.7 V; I²C V_OL 0.4 V

gate drive      3.3 − 0.4                       = 2.9 V   (1.4 V over the threshold)
state 3         3.3 > 0.4 + 0.7 + 1.5 = 2.6 V   → the low side reaches V_OL
sink            2.9/4.7k + 4.6/4.7k             = 1.60 mA (limit 3 mA)
far-side low    0.4 + 0.98 mA × 2 Ω             = 0.402 V (V_IL 1.5 V on the 5 V side)
rise, per side  0.8473 × 4.7k × 100 pF          = 398 ns  (Standard 1000 ns ok; Fast 300 ns not)
FET turn-off    4.7k × 100 pF × ln(3.3 / 1.5)   = 371 ns  before the 5 V side starts to rise

Fast-mode:      R ≤ 300 ns / (0.8473 × 100 pF)  = 3.54 kΩ;  R ≥ (2.9 + 4.6) / 3 mA = 2.5 kΩ  → 3.3 kΩ
1.8 V low side: gate drive 1.4 V < 1.5 V threshold → a sub-volt-threshold FET, or a TXS