ADC and DAC basics: what the datasheet numbers mean

An ADC turns a voltage into one of 2ⁿ codes; the datasheet says how far the part sits from that staircase. LSB, static errors, SNR and Nyquist, per TI SLAA013.

An analog-to-digital converter takes a voltage and returns a number; a digital-to-analog converter takes a number and returns a voltage. That much is in the names. What the datasheet is about is the distance between the number and the voltage — how many numbers there are, which one a given voltage gets, how wrong that mapping is at DC, how much worse it gets with frequency, and how often the conversion has to happen for the numbers to describe the signal at all. TI’s SLAA013, “Understanding Data Converters”, sets out those definitions with three-bit examples, and this article follows it: the ideal transfer function, the four static errors that describe every real one, the noise that quantization itself is, the timing limits, and sampling. The resolution calculator turns any datasheet’s lines into volts and bits; the noise floor calculator takes over where the dynamic specifications start.

What an ADC and a DAC are, exactly

SLAA013 defines the ADC by its output set: “an ideal ADC uniquely represents all analog inputs within a certain range by a limited number of digital output codes.” The transfer function “would be a straight line” if there were infinitely many codes; with 2ⁿ of them “the practical ideal transfer function is a uniform staircase”. Each step is one code, “the width of one step is defined as 1 LSB (one least significant bit)”, and it is “often used as the reference unit for other quantities in the specification” — an error of 2 LSB means two steps’ worth, whatever the step is in volts.

Two plots. Left: the ideal 3-bit ADC transfer function, a staircase of eight codes against analog input from 0 to 7 LSB, with a straight line through the centre of each step and a small sawtooth below showing the quantization error swinging between plus and minus half an LSB. Right: the ideal 3-bit DAC, eight dots on a straight line of analog output against digital input code. — Fig 1 — SLAA013's figures 1 and 2, redrawn for 3 bits. The ADC's "practical ideal transfer function is a uniform staircase": each code covers 1 LSB of input, the transitions sit half an LSB either side of the ideal line, and the difference between the input and the code's midstep value — the "inherent quantization error (± 1/2 LSB)" — is the sawtooth. The DAC is "a series of points that fall on the ideal straight line"; there is no quantization error in the output, only in whatever chose the code.

The step size is not quite range over 2ⁿ. “Since the first (zero) step and the last step are only one half of a full width, the full-scale range (FSR) is divided into 2ⁿ − 1 step widths”:

$1\ \text{LSB} = \frac{FSR}{2^n - 1}$

For 12 bits over 3.3 V that is 806 µV; for 8 bits over 5 V, 19.6 mV. And because the analog input is continuous and the codes are not, “there is a quantization process that introduces an error”: every input within a step gets the same code, so the code is wrong by up to half a step, the “inherent quantization error (± 1/2 LSB)”. An ideal ADC is an ADC that is wrong by that much and no more.

The DAC is the same staircase read the other way. “A DAC represents a limited number of discrete digital input codes by a corresponding number of discrete analog output values. Therefore, the transfer function of a DAC is a series of discrete points”; “1 LSB corresponds to the height of a step between successive analog outputs”. SLAA013’s picture of it is the one to keep: “a DAC can be thought of as a digitally controlled potentiometer whose output is a fraction of the full scale analog voltage determined by the digital input code.” A DAC has no quantization error of its own — its outputs are exactly on the line — but its input was quantized by whatever produced the code.

The four static errors

Real converters miss the staircase, and SLAA013’s claim is how little it takes to describe by how much: “static errors, that is those errors that affect the accuracy of the converter when it is converting static (dc) signals, can be completely described by just four terms. These are offset error, gain error, integral nonlinearity and differential nonlinearity. Each can be expressed in LSB units or sometimes as a percentage of the FSR. For example, an error of 1/2 LSB for an 8-bit converter corresponds to 0.2 % FSR.”

Four small plots of a 3-bit ADC staircase against the ideal one. Offset: the whole staircase shifted right by 1.25 LSB. Gain: the staircase stretched so the top code arrives 0.75 LSB late. DNL: one step, code 3, is half an LSB too wide and the next half an LSB too narrow. INL: the transitions bow away from the straight line by up to half an LSB in the middle. — Fig 2 — SLAA013's four static errors, drawn on a 3-bit ADC with the values its figures use: an offset of +1.25 LSB moves every transition by the same amount; a gain error of -0.75 LSB at full scale is "the same percentage error in each step"; a DNL of +0.5 LSB at code 3 is one step wider than 1 LSB (the next is narrower, since the range is fixed); INL is the bow of the transitions away from the end-point line. Absolute accuracy adds them, plus the ½ LSB of quantization.

Offset error is “the difference between the nominal and actual offset points” — for an ADC the input at which the output is zero, for a DAC the output for code zero. “This error affects all codes by the same amount and can usually be compensated for by a trimming process.”

Gain error is measured “after the offset error has been corrected to zero”: the difference at full scale, “a difference in the slope of the actual and ideal transfer functions”, so it “corresponds to the same percentage error in each step”. It, too, “can also usually be adjusted to zero by trimming” — or by the two-point calibration every firmware engineer has written.

Differential nonlinearity is the error in a single step: “the difference between an actual step width (for an ADC) or step height (for a DAC) and the ideal value of 1 LSB”. It has a hard limit. “If the DNL exceeds 1 LSB, there is a possibility that the converter can become nonmonotonic. This means that the magnitude of the output gets smaller for an increase in the magnitude of the input. In an ADC there is also a possibility that there can be missing codes.” A control loop closed through a non-monotonic DAC can sit on the reversal forever.

Integral nonlinearity is the accumulated bow: “the deviation of the values on the actual transfer function from a straight line”, where the line is by convention drawn “between the end points of the transfer function once the gain and offset errors have been nullified” — the end-point definition, “the usual definition adopted since it can be verified more directly”. The name is literal: “the summation of the differential nonlinearities from the bottom up to a particular step, determines the value of the integral nonlinearity at that step”. This is the one that calibration cannot remove, and the datasheet line that says what a converter is worth once the other two are trimmed out.

Absolute accuracy, or total error, “includes offset, gain, and integral linearity errors and also the quantization error in the case of an ADC”. The worked case in the calculator makes the point: a 12-bit converter with 1 LSB of offset, 2 of gain error and 1 of INL is wrong by up to 4.5 LSB before calibration, 3.6 mV on 3.3 V, and 4096 codes with 4.5 of uncertainty is about 8.8 bits of information. The twelve are real; so are the nine.

Quantization is noise, and it sets the SNR

The ± ½ LSB error is not a bug in the part; it is the conversion. SLAA013 treats it as what it is once the input is busy: “for the ideal staircase transfer function of an ADC, the error between the actual input and its digital form has a uniform probability density function if the input signal is assumed to be random”, spread evenly over ± q/2 where q is the step. The mean square of a uniform error is q²/12, and against a full-scale sine of amplitude A, with q = 2A / 2ⁿ, the ratio is

$SNR = 6.02\,n + 1.76\ \text{dB}$

“This gives the ideal value for an n bit converter and shows that each extra 1 bit of resolution provides approximately 6 dB improvement in the SNR.” Twelve bits is 74 dB; sixteen, 98 dB. The note also gives the floor under it: “the limit of a 1/2 LSB differential linearity error is a missing code condition which is equivalent to a reduction of 1 bit of resolution and hence a reduction of 6 dB in the SNR”, so the worst case is 6.02n − 4.24 dB. Where the 1.76 comes from, what a real converter loses to it, and why a datasheet’s SNR is quoted “over dc to f_s/2” is the noise floor article; the short version is that the formula is a ceiling, and reference noise, driver noise and clock jitter all pull the real number down.

Aperture: the clock is part of the resolution

An ADC does not read the input at an instant. The sample-and-hold switches from tracking to holding, and “aperture error is caused by the uncertainty in the time at which the sample/hold goes from sample mode to hold mode … This variation is caused by noise on the clock or the input signal.” During that uncertainty the input keeps moving, and the faster it moves the more the sample is wrong. SLAA013’s criterion: “if the aperture error is not to affect the accuracy of the converter, it must be less than 1/2 LSB at the point of maximum slew rate”, which for a full-scale sine is the zero crossing, 2πf·V_O. Solving:

$f_{max} = \frac{1}{T_A\,\pi\,2^{n+1}}$

With 1 ns of aperture uncertainty a 12-bit converter holds its resolution only below 39 kHz; a 16-bit one below 2.4 kHz. Every bit halves the frequency. This is the number that makes a clean sampling clock a precision component, and it is why a converter’s “MSPS” says nothing about the input frequency it resolves.

Sampling, Nyquist and aliasing

The last thing the datasheet assumes is that the input is sampled often enough. SLAA013 does the argument in the frequency domain: sampling “convolves the spectra of the input signal with that of the pulse train”, copying the input’s spectrum around every multiple of the sampling rate; “in effect some of the higher frequencies are folded back so that they produce interference at lower frequencies. This interference causes distortion which is called aliasing.” No overlap occurs when the sample rate is at least twice the highest input frequency — “this is Nyquist’s Sampling Theorem, and it provides the basic criteria for the selection of the sampling rate required by the converter to process an input signal of a given bandwidth.”

A plot of one millisecond of time. A fast sine wave at 8 kilohertz is drawn thin, with dots where it is sampled every 100 microseconds. A slower, inverted sine at 2 kilohertz, drawn bold, passes through every one of the same dots. — Fig 3 — Nyquist, SLAA013 §6: "if sampling is performed at a frequency at least twice as great as the maximum frequency of the input signal, no aliasing occurs". Here it is not: an 8 kHz sine sampled at 10 kS/s gives samples that a 2 kHz sine fits exactly (at 8 − 10 = −2 kHz, so with its phase inverted) — the "higher frequencies are folded back so that they produce interference at lower frequencies". Nothing after the converter can tell the two apart, which is why the anti-alias filter goes before it.

Two things follow that the theorem does not say. First, the samples of an aliased signal are indistinguishable from the samples of a legitimate one, so the protection has to be analog and in front of the converter: the anti-alias filter. Second, no filter is the “brickwall” the theorem wants — “in practice, this is approximated by a filter that introduces some attenuation in the passband, has a finite rolloff, and passes some frequencies in the stopband” — so the sample rate needs margin above twice the signal for the filter to work in. SLAA013’s filter chapter is the trade: Butterworth “maximally flat” and “by far the easiest to design”; Chebyshev sharper but with “poorer transient and step responses”; Cauer (elliptic) “the greatest roll-off”; Bessel-Thomson “designed to introduce no phase distortion but this is achieved at the expense of a poorer amplitude response”.

Reading a datasheet

The order to read a converter’s table in, from what is above:

Resolution, then INL. The bits are the code count; the INL is what is left after calibration. A 16-bit part with 8 LSB of INL is a 13-bit measurement.
DNL, for the number 1. Under it, monotonic and no missing codes; the datasheet usually says so in words.
Offset and gain error, to know what calibration will remove and whether the reference or the front end has to be trimmed too.
SNR, SINAD, ENOB, THD, SFDR — the dynamic table — against 6.02n + 1.76 dB, to see how much of the resolution survives at frequency. ADI’s MT-003 defines each; the noise floor calculator converts them.
Aperture jitter and the input bandwidth, against the highest frequency of interest.
Sample rate, last, with the anti-alias filter’s roll-off in mind.

Sources

TI, SLAA013 — Understanding Data Converters, 1995. The ideal ADC and DAC transfer functions, 1 LSB = FSR/(2ⁿ − 1), offset, gain, DNL and INL with the 3-bit figures, absolute accuracy, aperture error, quantization noise and SNR = 6.02n + 1.76 dB with the ½ LSB DNL worst case, ideal and real sampling, aliasing and the filter types.
ADI, MT-003 — Understand SINAD, ENOB, SNR, THD, THD + N, and SFDR. The dynamic specifications the static errors hand over to.