Why an op amp oscillates with a capacitive load

An op amp that rings, or oscillates outright, the moment a capacitor is connected to its output is not broken and is not unusual. TI’s stability white paper puts the mechanism in a sentence: “the load capacitance (C_LOAD) interacts with the output impedance of the amplifier (R_O), producing an additional pole in the amplifier’s A_OL curve”. Every real amplifier has that output impedance — “typically in the range of Ω to kΩ” — and every capacitor makes a pole with it. When the pole lands below the gain bandwidth, the loop gain reaches unity falling twice as fast as it should, the phase margin goes, and the output overshoots, rings, or in the worst case “an oscillation that is continuous and independent of the input signal”.

The fix that works nearly every time is a small resistor between the output pin and the capacitor, with the feedback still taken from the pin. TI’s SBOA418 gives a closed-form value for it from three datasheet numbers, and the capacitive load calculator computes that value along with the pole, the margin with and without it, the overshoot each margin implies, and what the resistor costs in bandwidth and DC drop. This article is the mechanism, the numbers, and the alternatives for when a plain resistor is not enough.

What the capacitor does to the loop

An amplifier’s open-loop gain A_OL is enormous at DC and falls at 20 dB per decade from its dominant pole until it reaches 1 at the gain bandwidth. Closing the loop through a feedback factor β — 1 for a buffer — gives the closed-loop gain SBOA418’s equation 1 describes, and it is well behaved as long as the loop gain A_OLβ crosses 0 dB with a comfortable phase left before −180°. That phase is the phase margin. SBOA626’s definition: “when A_OL × β(dB) = 0 dB the phase margin is the phase remaining before A_OL × β(phase_shift) = −180° and the circuit is unstable”.

A single dominant pole contributes 90° at most, so an unloaded amplifier crosses with about 90° of margin. The capacitor adds a second pole, SBOA418’s equation 3:

$f_{p2} = \frac{1}{2\pi R_O C_{LOAD}}$

Below the crossing it costs another 20 dB per decade of slope and up to another 90° of phase. SBOA418: “this additional pole (f_p2) causes the A_OL to decrease an additional 20 dB/decade resulting in a total of 40 dB/decade rate of closure with 1/β.” The rate of closure is the quick test — “a stable circuit exhibits a rate of closure of approximately 20 dB/decade” — and 40 dB per decade at the crossing is the signature of a load-capacitance problem.

The numbers in the figure are SBOA626’s own example: R_O = 100 Ω, 1 MHz of gain bandwidth, 10 nF on the output. The pole lands at 159 kHz — the paper says “158kHz” — well below the 1 MHz crossing, the loop reaches 0 dB at 383 kHz, and the phase left is 22.5°. Which amplifiers survive which loads follows directly: “for amplifiers with comparable bandwidth, an amplifier with lower open-loop output impedance is capable of driving larger capacitive loads, while maintaining stability”. A 10 µF reference capacitor on an OPA392, whose R_O is 120 Ω, puts the pole at 133 Hz against a 13 MHz bandwidth; SBOA418’s simulation finds “a phase margin of less than 1°”, and the model here gives 0.2°.

What the phase margin looks like on the bench

Phase margin is a loop quantity, but the paper’s point is that it can be read from the output without opening the loop. Apply a small square wave — “TI’s advice is to use a 10mVpp square wave to be certain that the input is small signal” — and measure the overshoot on the step: “there is a direct relationship between the percentage overshoot and the phase margins for second-order systems”. The relationship is the classic one between damping ratio and overshoot, and the benchmarks SBOA626 sets from it are the ones to design to:

Phase margin	Overshoot	SBOA626’s verdict
≥ 45°	< 23 %	“TI recommends a phase margin ≥ 45° for stable circuits”
35°–45°	23–34 %	“marginally stable, but can be acceptable in some cases”
30°	41 %	“some engineers accept a phase margin as low as 30° or 41 % overshoot”
< 35°	> 34 %	“unstable and leads to large overshoot, gain peaking, and oscillations”

Two cautions from the same section. The overshoot that reports phase margin is at the amplifier’s output pin: “to measure stability using AC gain peaking, the measurement must be made directly at the op amp output, not at the load”, because the resistor and the capacitor form a low-pass filter that hides the ringing at the load. And the reason to want more than the minimum is tolerance: “the parameters impacting stability (such as open-loop output impedance, open-loop gain, and external component values) all have tolerance, so generally, having a phase margin above 45° is advisable so the design is robust across process corners.”

The isolation resistor

The cure SBOA418 sizes is a resistor R_ISO in series between the output pin and the capacitor. It does two things. With C_LOAD it makes a zero — “this zero (f_z1) causes the A_OL curve to increase by 20 dB/decade, canceling out the effect of f_p2, and restoring the rate of closure to 20 dB per decade” — and it moves the pole down slightly, because the capacitor now sees R_O + R_ISO:

$f_{z1} = \frac{1}{2\pi R_{ISO} C_{LOAD}}, \qquad f_{p2}^{*} = \frac{1}{2\pi (R_O + R_{ISO}) C_{LOAD}}$

The question is where to put the zero. Too low and the resistor is large, which costs bandwidth and voltage; too high and it cancels the pole’s phase too late to help. SBOA418’s answer is to put it at the closure frequency, the point where the loaded gain would cross 1/β. On a log axis that crossing is the geometric mean of the pole and the gain bandwidth — “f_cl is always located at the midpoint between f_p2 and f_gbw on the logarithmic axis” — and setting f_z1 equal to it gives a quadratic in R_ISO whose positive root is the note’s equation 2:

$R_{ISO} = \frac{1 + \sqrt{1 + 8\pi R_O C_{LOAD} f_{gbw}}}{4\pi C_{LOAD} f_{gbw}}$

For SBOA626’s example that is 48.6 Ω, which the paper confirms as its “minimum R_ISO”: the zero at 327 kHz, the pole at 107 kHz, and its simulation reports 65.1° of phase margin where the single-pole model gives 66°. For the OPA392 reference buffer on 10 µF it is 384 mΩ: “implementing a small 380 mΩ isolation resistor in the OPA392 buffer circuit improves the phase margin to 60°, and the circuit is stable”. Fractions of an ohm, because the capacitor is enormous; the zero it needs is at 41 kHz.

Two rules go with the equation. SBOA626, on the parts bin: “when choosing a standard resistor value always round the resistance to a larger value”. And SBOA418, on trusting it: the equation assumes the amplifier is one dominant pole and a flat R_O, and “most op amps have additional poles and zeros near the unity gain bandwidth, so the phase margin is impacted by the secondary poles” — “always use Spice simulation tools such as TINA-TI to verify the circuit is stable and operating with the R_ISO value chosen”. The equation gets the resistor to within a step; the model or the bench confirms it.

Minimum or conservative

SBOA626 offers two design methods for the same resistor and is honest about the trade. The minimum-R_ISO method is the equation above: “provides the maximum bandwidth and has the minimum voltage drop when driving load impedances (V_DROP = I_L × R_ISO). However, the minimum R_ISO also has less tolerance to process, temperature, and component variation.” The conservative method places the zero a decade below the crossing instead — “this mostly cancels the effects of the pole, so the phase margin is approximately 90°” — and for the example lands on 181 Ω.

The step responses say what each buys: with no resistor “large overshoot and ringing”; with 48.6 Ω “a relatively small overshoot and good phase margin”; with 181 Ω “practically no overshoot and excellent phase margin”. The costs are on the next page. The resistor and the capacitor “form a low pass filter, so larger values of R_ISO reduces the bandwidth” — for the example, “from 602 kHz for R_ISO = 0 Ω to 107 kHz for R_ISO = 181 Ω”. And the drop: at 10 mA of load current, 48.6 Ω costs 0.49 V at the load and 181 Ω costs 1.8 V, none of which the amplifier corrects, because the feedback is taken from the pin.

When the resistor is not enough

The DC drop is the usual reason to want something else, and the answer is to close the loop at the load for DC while keeping it at the pin for high frequency. That is SBOA626’s dual-feedback method — a resistor R_F from the load side of R_ISO to the inverting input and a capacitor C_F from the output pin — and TI’s short SSZT999 compares it with the plain resistor on the bench. The plain R_ISO “displays a typical overdamped response with a moderate settling time”; adding the dual feedback “has a rounded single-lobe overshoot and long settling tail resulting in slower settling times than the R_ISO circuit”; adding a further resistor R_Fx in the feedback gives “a sharp single-lobe overshoot but settles very quickly”. Noise goes the other way: “the R_ISO circuit has the lowest noise”, and the R_Fx version “the highest noise because of the increase in noise gain at higher frequencies”.

Noise gain is itself a compensation. A higher closed-loop gain lowers the frequency at which the loop crosses 0 dB, which moves the crossing away from the load pole; the same 10 nF that leaves 22.5° in a buffer leaves 61° at a gain of ten, with no resistor at all. SBOA626’s §4.4 uses this deliberately, raising the noise gain at high frequency without changing the signal gain. Its §4.3 covers the series RC snubber across the load for power amplifiers, and §4.5 the feedback capacitor. And its chapter 5 is a warning that not every oscillation is this one: capacitance on the inverting input puts a zero in 1/β rather than a pole in A_OL, and its fix is a feedback capacitor, which does nothing for a load capacitance.

Reading the datasheet instead

Most of this is already on the datasheet, in the plot of small-signal overshoot or phase margin against capacitive load. SBOA626’s example is the OPA192 as a buffer: “the maximum capacitive load for 20 % overshoot and R_ISO = 0 Ω is about 200 pF. For a 50 Ω isolation resistor, the circuit can drive capacitances well beyond 1 nF and still keep overshoot less than 20 %.” The plot’s curves for different isolation resistors are the vendor’s version of the calculation above, done with the real model. Two things to check before using one: the gain — “the graphs also specify the op amp configuration used to drive the capacitive load because the configuration affects the stability”, and a G = +1 curve does not apply to a G = +10 stage — and whether the plot is at the output pin or the load.

When there is no plot, there is still R_O. SBOA418 reads the OPA392’s from the electrical characteristics table, “120 Ω” at 1 MHz, and from the open-loop output impedance plot, “which is flat at approximately 120 Ω across frequency”. The method needs the second fact as much as the first: “the analysis in this document applies to amplifiers that have a flat, resistive output impedance across the effective bandwidth of the amplifier”. An amplifier whose Z_O rises inductively at high frequency, or falls, is SBOA626’s chapter 6, and its resonances with the load need the model.

Where the model stops being valid

• The margin is an estimate. The single-pole model reproduces SBOA626’s example to within a degree and lands SBOA418’s OPA392 case at 52° where the simulation says 60°; that gap is the real amplifier’s higher-order poles. Design with the equation, confirm with the model or a 10 mV step.
• R_O is a typical value. It changes with process, temperature and load current, and a margin designed to 45° at typical can be 35° at a corner. The conservative resistor, where the bandwidth and the drop allow it, is the one that survives.
• The load is not always a capacitor. A cable is a transmission line; a MOSFET gate is a capacitance that changes with voltage; a SAR ADC’s input is a switched capacitor whose charge-bucket kick is a different problem from its DC loading.
• Feedback from the wrong side undoes the fix. The zero exists because the feedback sees the output pin and the capacitor is outside the loop. Feedback from the load side of R_ISO puts the RC back inside it and restores the pole.

Sources

• TI SBOA418, “Determine Optimal Isolation Resistance for Driving Capacitive Load” (2023): the pole, the zero, the closure frequency and equation 2; the OPA392 example.
• TI SBOA626, “Operational Amplifier Stability Theory and Compensation Methods” (2025): phase margin and overshoot benchmarks, the §4.1 worked example, the minimum and conservative R_ISO methods, dual feedback, noise gain, snubber and feedback-capacitor compensation.
• TI SSZT999, “Do-it-yourself: three ways to stabilize op amp capacitive loads” (2017): the three circuits compared on step response and noise.