How to choose and place a TVS diode for ESD protection

The selection rule fits in three lines: pick V_RWM at or above the highest voltage the line legitimately carries, then check the clamping voltage at the real strike current — not the working voltage — against the absolute maximum of the pin behind it, and check the capacitance against the data rate. The placement rule is shorter still: the TVS goes at the connector, on the same copper layer as the connector, with its ground pin stitched straight into the plane, so the strike is shunted before it ever travels into the board.

Both halves matter equally, and the second is the one that gets skipped. TI’s layout guide, SLVA680, is blunt about where the leverage is:

Since the designer has no control over I_ESD, lowering the impedance to ground is the primary means available for minimizing V_ESD.

The current is fixed by the standard. The diode fixes the first ten volts or so. Everything above that is inductance you drew.

The three voltages on the datasheet

A TVS datasheet leads with a working voltage — “5 V”, “24 V” — and that number says nothing about what the protected pin sees during a strike. Three voltages matter, and TI’s guide to reading these datasheets, SLLA305, defines them precisely:

• V_RWM, the reverse stand-off (working) voltage: the highest voltage the line can sit at with the diode effectively absent. SLLA305’s example part specifies it at 5.5 V with leakage below 100 nA.
• V_BR, the breakdown voltage: where the diode starts to conduct significant current, defined at 1 mA. The same part: 7 V minimum, 8 V typical, 9 V maximum.
• V_CLAMP, the clamping voltage: the voltage across the diode — and therefore at the protected pin — while it is carrying the strike current. The same part again: 7.6 V at 1 A, 8.2 V at 5 A, 10.4 V at 16 A.

So the “5 V” TVS is a 10.4 V part during the event it exists for. That is not a defect; it is how a clamp works. The failure is reading V_RWM as the protection level and wiring it in front of a pin whose absolute maximum is 6 V.

The other classic misreading goes the opposite way, and TI’s surge-selection note SLVAE37 calls it out directly:

A common mistake is thinking that since V_BR is where the diode begins to conduct significantly, nominal system voltages below V_BR will assure low leakage. This is not the case, as V_BR can shift and has a relatively high defined leakage at 1 mA.

Size the working voltage by V_RWM, never by V_BR. If the line runs at 5 V nominal but can excurse to 7 V, SLVAE37’s rule is that V_RWM must be 7 V or greater — the excursion, not the nominal, is what must not leak.

What an 8 kV strike actually delivers

The reference event is the IEC 61000-4-2 contact discharge, and its Level 4 — 8 kV — waveform is the one SLVA680 opens with: a current spike peaking at 30 A with an 800 ps 90/10 rise time, followed by a broader hump, the whole thing over within about 100 ns.

Two numbers from that waveform organise everything that follows. The first is the slew rate of the leading edge, which SLVA680 computes:

$$\frac{dI_{ESD}}{dt} = \frac{30\ \text{A}}{0.8 \times 10^{-9}\ \text{s}} \approx 4 \times 10^{10}\ \text{A/s}$$

That figure is why layout dominates: any inductance in the shunt path is multiplied by it.

The second is the current in the body of the pulse. SLLA305 gives the equivalence table between IEC strike levels and the transmission-line-pulse (TLP) currents used to characterise clamps: 2 kV corresponds to 4 A, 4 kV to 8 A, 6 kV to 12 A, and 8 kV to 16 A — which is why “for most ESD devices, the clamping voltage is specified at 16-A/8-kV IEC”. When a datasheet quotes V_CLAMP at 16 A, it is quoting the 8 kV number.

Dynamic resistance is the number that compares parts

Above breakdown, a TVS is close to a battery in series with a small resistor. SLVAE37 writes the model in one line:

$$V_{CLAMP} = V_{BR} + I_{SURGE} \cdot R_{DYN}$$

R_DYN, the dynamic resistance, is the slope of the I-V curve in conduction — in SLLA305’s words, it “characterizes the steepness of the device’s I-V curve”, and minimising it “usually provides better clamping voltage and protection”. The example part’s whole clamping table is one line with slope 0.19 Ω:

One detail of that line matters to anyone who reads V_BR off the DC table and extrapolates from it. Drawn through the pulsed points with the datasheet’s 0.19 Ω, the line meets zero current at about 7.4 V, not at the 8 V breakdown: the 1 mA DC breakdown and the intercept of the TLP line are two different measurements (the same table lists a 7.2 V TLP holding voltage), and pinning the line at V_BR would put the 16 A clamp at 11 V against the 10.4 V the table states. Extrapolate from a published clamping point, as the TVS clamping calculator does, rather than from V_BR.

This is also the honest way to compare parts across vendors, because datasheets quote V_CLAMP at whatever current flatters them. SLLA305’s method: take the TLP plot — a rectangular pulse of 1 to 5 ns rise time and 100 ns width, swept in amplitude — read the clamping voltage at the current that matches the strike level you care about, and if R_DYN is not printed, recover it from any two points. SLVAE37 gives the rearrangement:

$$R_{DYN} = \frac{V_{CLAMP} - V_{BR}}{I_{SURGE}}$$

Two cautions from the sources. First, both quantities are only meaningful against a named waveform — a V_CLAMP specified for a 100 ns TLP pulse and one specified for an 8/20 µs surge are different measurements, and SLVAE37 is explicit that there is no easy conversion between waveforms; match the test condition or find a part specified at yours. Second, the spread is enormous: SLLA305’s worked TLP reading for a CAN-bus protection part (the ESD2CANFD24) lands at an estimated 36 V at 16 A, against the 5 V part’s 10.4 V. Same strike, same current — the difference is V_BR plus dynamic resistance, and nothing on the front page of either datasheet reveals it.

Capacitance is the price of protection

The clamp is a diode junction, and its depletion region is a capacitor hanging on the line. SLLA305 does not soften the consequence:

With high speed data applications, a low capacitance is required to maintain signal integrity or the signal can be distorted beyond recognition.

The numbers span four orders of magnitude. SLLA305’s example ESD parts sit at 0.5 pF (ESD451) and 1.6 pF (ESD751); SLVAE37’s 33 V surge diodes at 100 pF to 200 pF; and for low-voltage surge parts, SLVAE37 warns that “leakages can rise to close to 1 mA and capacitances are often above 1000 pF”. A shunt capacitance on a matched 50 Ω line makes the cost concrete:

SLLA305’s rule of thumb for reading an insertion-loss plot is that the device supports the signal while the loss is between 0 and −3 dB — its example low-capacitance part holds that to 5 GHz. A 1000 pF surge diode on the same plot has given up before 10 MHz. This is why the surge-rated part protecting a power input and the sub-picofarad part protecting a data pair are different components, and why a protection budget starts with the data rate.

ESD or surge: decide which event sizes the part

The two IEC events are routinely conflated and are different problems. IEC 61000-4-2 ESD is nanoseconds and tens of amps: fierce dI/dt, little total energy. IEC 61000-4-5 surge — the environment SLVAE37 addresses, “large transient spikes that are caused by nearby machinery, lightning strikes, or power surges” — is the 8/20 µs waveform: a comparable current sustained for three orders of magnitude longer, which SLLA305 characterises as “large increases in current for a duration in the µs range” with “significant amounts of energy”.

The consequence for sizing comes from what actually kills the diode:

Note that TVS diodes fail due to excess current rather than excess voltage, so when selecting a TVS diode I_PP, the surge current magnitude determines the requirement.

I_PP — the peak pulse current the diode survives — is therefore quoted against a waveform, almost always the 10/1000 µs pulse, sometimes the 8/20 µs one, and the same die is rated very differently against each: the shorter the pulse, the higher the rating. SLVAE37 adds the derating trap: many TVS diodes derate significantly — up to 80 % of their nominal value — when raised to 105 °C or 125 °C, so the number that matters is I_PP at the operating temperature, read off the derating curve.

Which event applies is a question about the connector, not the diode. A USB port a person walks up to is an ESD problem. A 4/20 mA loop, or an RS-485 bus leaving the building on hundreds of metres of cable, is surge territory — SLLA305’s list of what raises the exposure is “outdoor operation, long cabling, frequent load changes”. Interfaces exposed to both need a part rated for both, and the surge rating is the one that sets the die size.

Sizing for surge: TI’s worked example

SLVAE37 walks the whole selection once, and the numbers are worth following because the first candidate fails in a way a datasheet front page would never show. The input is a PLC 4/20 mA line: nominal 24 V, up to 33 V DC, protected circuitry rated to 60 V absolute maximum, 85 °C environment, and a ±1 kV IEC 61000-4-5 surge coupled through 40 Ω — which with 2 Ω of source is 1000 V / 42 Ω ≈ 24 A of surge current.

V_RWM must be 33 V or greater; three candidates qualify, all with V_BR around 36–38 V. Then R_DYN separates them:

• SMAJ33A, R_DYN 884 mΩ: clamps at 38.6 V + 24 A × 0.884 Ω = 59.8 V at 25 °C. Applying the datasheet’s temperature coefficient of 10 × 10⁻⁴ /°C over the 60 °C rise gives 63.4 V at 85 °C — through the 60 V absolute maximum. It also fails on energy: the required dissipation is 24 A × 63.4 V = 1543 W, against roughly 1150 W of temperature-derated 8/20 µs capability.
• SMBJ33A, R_DYN 504 mΩ: 51.1 V nominal, 54.2 V maximum — inside the window, with 1299 W required against about 2000 W derated. Workable, with margin.
• TVS3300, R_DYN 60 mΩ maximum: clamps below 39 V, needs only 936 W, absorbs 32 A at 85 °C, and its datasheet specifies 4000 strikes of 30 A at 125 °C. The low R_DYN is doing all of that at once — lower clamp, lower energy, more margin.

Three parts with the same working voltage and nearly the same breakdown voltage, separated by an order of magnitude in what the protected pin experiences. That is what “comparing parts honestly” means: compare V_BR + I·R_DYN at your current, your waveform, your temperature.

Placement: the TVS belongs at the connector

Now the second half, which decides whether the part you just chose performs anywhere near its datasheet. SLVA680’s model is worth internalising: the TVS protects by being the lowest-impedance path to ground at the point where the strike enters. Every design decision either preserves that or spends it.

The first rule is position. Place the TVS as near to the connector as the design rules allow, and place the protected IC far from both — SLVA680 suggests near the middle of the board. The reasoning is inductive steering: with the diode adjacent to the entry point and the IC distant, the inductance beyond the tap (L4) is much larger than the inductance before it (L1), and the strike current divides overwhelmingly into the diode.

The anti-pattern is the TVS on a stub — a branch off the protected line down to a diode parked wherever there was room. SLVA680’s instruction:

Do not use stubs between the TVS and the Protected Line, route directly from the ESD Source to the TVS.

On a stub, the diode still clamps, but the stub’s inductance is now in series with the clamp, and the protected line runs on unclamped in parallel.

The loop, drawn as four inductances

SLVA680 reduces the whole layout problem to four parasitic inductors around a single-channel TVS, and one equation:

$$V_{ESD} = V_{br\_TVS} + I_{ESD} \cdot R_{DYN(TVS)} + (L_2 + L_3) \cdot \frac{dI_{ESD}}{dt}$$

L1 and L4 are the trace either side of the tap; they steer, and only L4 being large helps. L2 is the stub, which a correct layout eliminates entirely. L3 is the path from the TVS to ground, and SLVA680 singles it out:

The inductor at L3 represents the inductance between the TVS and ground. This value should be reduced as much as possible, and perhaps represents the most predominant parasitic influencing V_ESD.

This is the same argument that runs through decoupling — the component’s performance is the loop it sits in, which is why layout alone was worth 40 dB in a decoupling filter with identical parts. Here the loop is: connector pin, trace, TVS, ground pad, plane, back to the connector shell. The diode is one segment of it.

Every nanohenry in the shunt path costs 40 V

Put the two quoted numbers together and the sensitivity falls out. The slew rate is 4 × 10¹⁰ A/s. SLVA680’s example inductance is 0.25 nH — a couple of millimetres of trace or a fraction of a via:

$$V_L = L \cdot \frac{dI_{ESD}}{dt} = 0.25\ \text{nH} \times 4 \times 10^{10}\ \text{A/s} = 10\ \text{V}$$

Ten volts, from a quarter of a nanohenry, on top of the clamp. Scale it: one nanohenry — one short trace neck, one ordinary via — adds 40 V. Stacked on SLLA305’s 10.4 V clamp:

This is the number to hold in mind when the layout review reaches the protection circuit. The difference between a 10 V event and a 50 V event at the protected pin is not the diode — it is roughly one nanohenry of routing. No selection spreadsheet recovers what a long ground stitch gives away.

No layer change between connector and TVS

A via is inductance, and where it sits in the protection path decides whether that inductance is harmless or ruinous. SLVA680:

Generally, placing a VIA between the ESD Source and the TVS is detrimental, but in some circumstances the designer is forced to do so.

The note draws three cases:

In Case 1 the connector-to-TVS run stays on one layer and the via comes after the diode, where it merely adds to L4 and helps the steering. In Case 2 the via sits in the branch to the TVS: the strike divides at the tap, the protected IC “may take the brunt of the current”, and whatever does reach the diode pays L_VIA · dI_ESD/dt on the way. Case 3 is for when the diode genuinely cannot live on the connector’s layer: the connector’s trace goes through a via straight to the TVS pad, and the path onward to the IC leaves the pad through a second via. The via inductance is now paid in full, in series with the strike — but there is no branch before the clamp, so the current is forced through the diode before it has any path onward. SLVA680 calls it “an acceptable compromise to Case 2”, acceptable “if there is no alternative”.

The rule that survives contact with a real board: route the protected line from the connector directly to the TVS pin — on one layer wherever possible, and through a via that leads nowhere else if not; everything after that pin is negotiable.

The ground return decides the clamp you actually get

L3 — the diode-to-ground leg — is where SLVA680 spends its grounding chapter, because eliminating every other parasitic achieves nothing “without a very low impedance path to ground for the TVS”. The prescription:

• The TVS ground pin lands on a same-layer ground pour, coupled to a plane on the immediately adjacent layer.
• The pour is stitched with vias, one of them immediately adjacent to the TVS ground pad; the plane is not broken anywhere near it.
• A chassis screw to earth sits near both the TVS ground and the connector shell, so the discharge returns to the shell where it entered rather than wandering the board as a ground shift under every protected IC. Where no chassis earth exists, tightly coupled ground planes are the fallback.

The ground via itself gets engineering attention: SLVA680 asks for the largest practical pad and drill — at ESD edge rates the skin effect makes the via’s surface area, inside and out, the conducting cross-section — filled with non-conductive epoxy so the drill’s inner surface survives, and plated over at the pad. (For the DC side of a via’s life — resistance and current capacity from drill and plating — the via calculator runs the numbers; the ESD argument is about surface, not cross-section.)

Keep everything else out of the strike zone

Until the current reaches the diode, the trace carrying it is an antenna driven at 4 × 10¹⁰ A/s. SLVA680 treats the region between connector and TVS as radioactive:

the PCB designer should consider this region a Keep-Out area for unprotected PCB traces which could damage the system by either having direct contact with an IC, or by carrying the EMI further into the system where it could radiate more EMI.

So: no unprotected lines routed alongside the connector-to-TVS run — on any layer a via in that run crosses. Keep the run short and straight. Where corners are unavoidable, curve them with the largest radius the tools allow, and never exceed 45°: SLVA680’s field simulation of a 90° corner during an 8 kV event shows at least 7 kV at the corner, enough to arc in air across anything closer than about 2.6 mm, and its crosstalk plot shows the 90° corner coupling far more than the 45° or curved versions exactly in the ESD frequency band. After the TVS, the trace to the protected IC should be comparatively quiet — which is one more reason the diode goes first.

The selection flow

Everything above compresses into an order of operations:

Threat first, because the waveform fixes the current and the current fixes every later comparison. Then the voltage window — V_RWM above the operating voltage, clamp below the pin’s absolute maximum, both evaluated with V_BR + I·R_DYN at the real current and temperature. Then survival: I_PP against the same waveform, derated. Then the parasitics, capacitance against the data rate and leakage against the power budget. Then polarity — bidirectional if the signal legitimately goes negative, at the cost of a higher negative clamp. And then the placement, which is not a downstream detail but the second half of the specification: at the connector, no stub, no layer change, ground stitched tight. A perfectly chosen TVS at the wrong end of two nanohenries clamps eighty volts higher than the datasheet says.

Sources

• TI SLVA680 — ESD Protection Layout Guide — the IEC 61000-4-2 waveform and its 4 × 10¹⁰ A/s slew rate, the four-inductance model, the 0.25 nH → 10 V example, the three via cases, corner EMI, and the ground-return scheme.
• TI SLLA305 — Reading and Understanding an ESD Protection Data Sheet — V_RWM, V_BR, V_CLAMP and R_DYN definitions, the example electrical-characteristics table, the IEC-to-TLP equivalence, the TLP method, and the capacitance and insertion-loss guidance.
• TI SLVAE37 — How to select a Surge Diode — the clamp equation, IEC 61000-4-5 surge sizing, I_PP waveform dependence and temperature derating, polarity, parasitics, and the worked PLC input selection.

Updates

• 2026-09-13 — Fig 10 redrawn. Case 3 previously showed the TVS on the connector’s layer with the via after it, which is Case 1 over again. SLVA680’s Case 3 puts the TVS on a different layer, reached through a via that leads only to its pad, with a second via onward to the IC; the paragraph on Case 3 now says the same.
• 2026-09-13 — Fig 1 and Fig 3 now describe the conduction line as what it is: a line through the datasheet’s TLP points, meeting zero current near 7.4 V, rather than a line starting at the 8 V, 1 mA DC breakdown — which it never did. A paragraph after Fig 3 explains why the two differ and why extrapolation starts from a clamping point, not from V_BR.
• 2026-09-13 — Fig 2 and Fig 5: the ESD pulse model’s time constants are now solved so its 10–90 rise is the 800 ps it is labelled with (the earlier curve rose in about 460 ps), and the 8/20 µs surge now has an 8 µs front time and 20 µs to half value (its front was roughly twice too fast).
• 2026-09-13 — The “outdoor operation, long cabling, frequent load changes” list is SLLA305’s, not SLVAE37’s; attribution corrected. The 16 A at 30 ns behind Fig 2 is the IEC waveform’s reference point, not something SLLA305 derives; the caption now says so.
• 2026-09-13 — 30 A / 0.8 ns is 3.75 × 10¹⁰ A/s; the slew rate is now written as ≈ 4 × 10¹⁰ A/s, which is SLVA680’s rounding. Fig 4, Fig 6 and Fig 11 redrawn to clear a label struck by a curve, make faint curves legible in dark mode, and move a label off the pour edge.