Buck converter input filter design for conducted EMI

The whole design hangs on one number at one frequency. Measure — or estimate — the conducted noise at the switching fundamental, subtract the limit line that applies to your product, and the difference in dB is the attenuation the input filter owes. Everything above the fundamental falls faster than the filter’s own rolloff, so a filter that fixes the fundamental fixes the harmonics for free.

From there the procedure in TI’s AN-2162 is four steps: pick the filter inductor L_f in the 1–10 µH range, as large as current rating and size allow; compute the filter capacitor C_f from two formulas and take the higher; then damp the LC’s resonant peak with an electrolytic of at least 4 × C_IN whose ESR is about √(L_f/C_IN). The rest of this article is why each step is what it is — where the pulsed current comes from, what the LISN in the test lab actually measures, why the undamped filter is a hazard to both the measurement and the converter’s own control loop, and a worked example run end to end on TI’s published numbers from SNVA755.

A buck’s input current is a square wave

A buck converter’s inductor smooths the output. Nothing smooths the input. During the on-time the high-side switch connects the inductor to the input rail and the converter draws the full inductor current; during the off-time the switch opens, the diode or low-side switch carries the current, and the input sees nothing. AN-2162 states it as the defining property of the topology:

Conducted EMI arises from the normal operation of switching circuits. The ON and OFF actions of the power switches generate large discontinuous currents. The discontinuous currents are present at the input side of buck converters, the output side of boost converters and at both input and output ports of flyback and buck-boost topologies.

So the output side is usually already handled by the converter’s own LC — that side has its own failure modes, but they are ripple problems, not compliance problems. The input side is where a buck fails conducted emissions.

For analysis, AN-2162 flattens the ripple on top of the pulse and treats the input current as a square wave of height I (the DC inductor current, which equals the output current in a buck) and duty cycle D. That approximation is what makes the spectrum tractable, and it is good enough to size a filter before any measurement exists.

Two consequences fall straight out of the geometry. First, the noise scales with current, not voltage:

Conducted EMI involves the normal operation of DC-DC converters. It does not involve circuit parasitics except input or output capacitor ESR and ESL. PCB layout itself is not going to help reduce conducted EMI. Further, conducted EMI is only related to the current level, not the voltage level at input or output ports.

Second — same paragraph — a lower input voltage at the same output power means higher input current, and therefore worse conducted EMI. The 12 V version of your product will emit more than the 24 V version.

The ripple it leaves across the input capacitor

The input capacitor C_IN supplies the AC difference between the pulse and the average. It does so imperfectly: its impedance at the switching frequency turns the discontinuous current into a ripple voltage, and that ripple is what conducts out of the leads. The fundamental of that ripple sits at the switching frequency, with harmonics above it.

The shape of that spectrum is why the design anchors at the fundamental. The square wave’s Fourier amplitudes fall as 1/n; the capacitor’s impedance falls as 1/n again; the product falls as 1/n², about 40 dB per decade. A low-pass filter steepens that further. AN-2162 draws the conclusion plainly:

The low pass filter provides even greater attenuation for the higher order harmonics of the switching frequency. The switching frequency attenuation is the worst case condition and is the focus of the filter design.

Both notes assume C_IN is a low-ESR ceramic, and the exception clause above — “except input or output capacitor ESR and ESL” — is worth a pause. A capacitor is only a capacitor below its self-resonance; above it, the ESL takes over and the 1/n impedance rolloff stops. The clean 1/n² envelope is the ceramic-input story, and it is one reason the application notes insist on that capacitor type.

What the compliance test actually measures

Conducted emissions are not measured by probing your board. They are measured by inserting a defined network — a Line Impedance Stabilization Network — between the power source and the equipment under test:

The LISN is connected in series with the power input lines to the SMPS under test. The LISN establishes consistent source and measurement impedance allowing for repeatability of test results.

That is the whole point: your bench supply’s output impedance is an accident of its design and its cable, so a limit specified against it would be meaningless. The LISN replaces the accident with a standard.

Inside each line: a 50 µH series inductor isolates the source, a 1 µF capacitor on the source side shunts what leaks past it, and a 0.1 µF capacitor blocks the supply DC while coupling the noise into the 50 Ω spectrum analyzer input, with a 1000 Ω resistor holding the tap when the analyzer is switched to the other line. For differential-mode analysis of a two-line DC-DC converter, AN-2162’s equivalent circuit collapses the pair to 100 µH, 0.5 µF and 100 Ω across the measured noise voltage.

The practical advice in the note is the kind that saves a wasted afternoon: power the test from a battery (with a fuse) so the source itself is quiet, scan Line 1 and Line 2 separately and keep the worse result, expect roughly ten minutes per scan, disconnect the analyzer input before flipping the line selector so the DC step through the blocking capacitor does not damage it, and do not coil the leads:

Tightly coiled power cords may contribute series cable inductance that may falsely lower the analyzer reading.

A non-isolated two-line converter has no third conductor to carry common-mode current in this model — AN-2162 defines V_COMM as the in-phase half of the two line voltages and notes that with only two lines it is always zero — so everything that follows is about the differential-mode noise between the lines.

Required attenuation: the gap between the fundamental and the limit

Which limit applies is a market question, not an engineering one. AN-2162 names the European norms (EN55022 and so forth) and FCC Part 15 in the USA; SNVA755’s worked design targets CISPR 22 Class B. The measurement span runs up to 30 MHz — AN-2162 gives it as starting at 10 kHz, SNVA755 as 150 kHz, the difference being which standard is invoked. The plots carry both quasi-peak and average limit lines; the analyzer manual tells you which detector you are looking at.

Whatever the limit, the required attenuation is defined the same way:

The height of the fundamental above the target limit line establishes the required additional filter attenuation needed in order to comply with the desired limit.

Before a certified measurement exists, AN-2162 offers two estimates. Method 1 is a wideband oscilloscope on the input ripple:

$$|\mathrm{Att}|_{\mathrm{dB}} = 20 \log\!\left(\frac{V_{in\text{-}ripple\text{-}p2p}}{1\,\mu\mathrm{V}}\right) - V_{max}$$

where V_max is the level the standard allows at the switching frequency, in dBµV. Method 2 needs no measurement at all: take the first Fourier harmonic of the square-wave input current, (2I/π)·sin(πD), multiply by the impedance of C_IN at the switching frequency, 1/(2π·f_s·C_IN), and the product is the unfiltered fundamental:

$$|\mathrm{Att}|_{\mathrm{dB}} = 20 \log\!\left(\frac{I \cdot \sin(\pi D)}{\pi^2 f_s\, C_{IN} \cdot 1\,\mu\mathrm{V}}\right) - V_{max}$$

For the SNVA755 operating point — 3 A of inductor current, D ≈ 5/24, 420 kHz, 9.62 µF — that predicts a fundamental around 93 dBµV, which is the number behind Fig 2. The estimate exists so the first prototype can carry a filter that is approximately right; both notes expect an iteration after the first real scan.

The filter is designed from right to left

The filter is a series inductor and a shunt capacitor between the source and the converter. The direction matters, and AN-2162 flags it because it is easy to get backwards:

Note the EMI filter configuration is actually from the right to the left. In other words the filter “ac input” is VB and the filter “ac output” is VA.

The noise source is the converter. The thing being protected is the supply line. So the filter’s input is the converter-side node V_B — where the damping branch joins the converter’s own C_IN — and its output is the source-side node V_A, which the LISN observes and which C_f shunts. Read from the converter outwards, the filter is a π: C_IN first, then L_f, then C_f in front of the measurement.

The inductor comes first, and bigger is better

AN-2162 disposes of the inductor in three sentences:

The inductor defines the resonant frequency of the EMI filter hence its value (Lf) is usually in the range of 1 µH to 10 µH for low and medium power applications. Choose the highest value in compliance with amperage and physical size requirements.

SNVA755 widens the range to 1–20 µH and chooses a 12 µH part (1234AS-H-120M: 12 µH, 1 A, 0.19 Ω) for its 3 A, 420 kHz design. The logic of “highest value that fits” is that every microhenry of L_f pushes the corner frequency down and buys attenuation without demanding more capacitance — the constraint is the DC current the part must carry without saturating, and the board area it costs.

Two formulas for C_f — take the higher

With L_f fixed, the capacitor is computed twice:

$$C_{fa} = \frac{C_{IN}}{C_{IN}\, L_f \left(2\pi f_s/10\right)^2 - 1} \qquad C_{fb} = \frac{1}{L_f}\left(\frac{10^{\,|\mathrm{Att}|_{\mathrm{dB}}/40}}{2\pi f_s}\right)^2$$

The first formula ensures that the resonance frequency of the EMI input filter is at least one decade below the switching frequency. The second formula is derived from an approximation that ensures proper attenuation of the EMI filter. Select the higher value of Cfa and Cfb because both conditions must be met.

The decade-below rule is doing two jobs at once: it keeps the filter’s resonant peak far from the switching fundamental it must attenuate, and it guarantees the −40 dB/decade region has a full decade to work in before the fundamental arrives. The second formula is just that slope run backwards from the required attenuation: a two-pole filter gains 40 dB per decade, so 10^(|Att|/40) is the frequency ratio needed between corner and fundamental. The first formula is the same kind of rule with the topology written into it: solved for the resonant frequency, it places L_f against C_f and C_IN in series — the loop that C_f, L_f and C_IN form — at exactly f_s/10. It only comes out that way with C_f on the source side of the inductor.

For the SNVA755 design the arithmetic lands at C_fa = 1.37 µF and C_fb = 2.1 µF; the board carries 4.7 µF ∥ 0.22 µF, comfortably above both. The corner of Fig 6 sits near 21 kHz, twenty times below 420 kHz; the C_fa criterion itself — L_f against C_f in series with C_IN — lands near 25 kHz for the chosen capacitor, still well under the 42 kHz it demands. The computed response gives about 52 dB at the fundamental against the 45 dB required.

The undamped filter peaks exactly where it hurts

Fig 6 contains a warning as well as a result: at the corner frequency the response is not flat, it gains — about +18 dB for these values, because the only loss in the circuit is the inductor’s 0.19 Ω DCR. An LC filter with nothing to dissipate into is a resonator. This is the same mechanism that lets a ferrite bead in front of a capacitor amplify the very noise it was meant to remove; here the resonance is deliberate and placed a decade below the switching frequency, but it does not stop existing because it was placed on purpose. The ferrite bead filter calculator shows where that peak lands for a given bead and capacitor.

The quantity the application notes actually worry about is the filter’s output impedance at V_B. Looking back from V_B toward a stiff source, C_f sits directly across that source and drops out; what remains is L_f resonating with C_IN — the “filter formed by CIN and Lf” in the note’s words — which peaks near 15 kHz here, just below the corner of Fig 6:

Added damping is needed when the output impedance is very high at the resonant frequency (that is, Q of filter formed by CIN and Lf is too high.)

Computed for the SNVA755 values, the undamped peak reaches about 6.7 Ω. Add the damping branch the next section describes and the same curve tops out near 1.0 Ω. The resonant frequency barely moves; the energy that used to circulate now has somewhere to die.

Damping: one electrolytic, sized by two lines

AN-2162’s prescription is a capacitor in series with a resistance, across V_B:

$$C_d \ge 4\, C_{IN} \qquad ESR_d \approx \sqrt{L_f / C_{IN}}$$

The capacitance must be large enough to look like a short at the resonant frequency — that is what “at least four times C_IN” buys — and the resistance is the loss that flattens the peak, set near the characteristic impedance of the LC so it damps effectively without spoiling the filter’s corner. The elegant part is what the capacitor is for:

The purpose of ESRd is to reduce the peak output impedance of the filter at the cutoff frequency. The capacitor Cd blocks the dc component of the input voltage, and avoids excessive power dissipation on ESRd.

A resistor alone across the rail would burn DC continuously. In series with C_d it sees only ripple. And an aluminium electrolytic supplies both parts in one can — its ESR, a defect everywhere else, is the damping element here. AN-2162 adds the ratings detail: the electrolytic’s DC voltage rating should be at least 25 % above the worst-case maximum source voltage.

For the worked case, C_d ≥ 38 µF and ESR_d ≈ 1.1 Ω. SNVA755’s own board, as it happens, omits the electrolytic to save cost — a legitimate choice the note makes explicitly, not an oversight — and its two design examples in AN-2162 carry 150 µF and 100 µF damping capacitors respectively.

The filter can destabilise the converter it protects

The damping section exists because of a second, quieter failure mode, and AN-2162 names it before it ever discusses EMI performance:

Another aspect of the design of the LC stage is that large values of Lf and small values of CIN can lead to input instability on the SMPS with accompanying adverse effects on the normal operation of the supply.

Addition of an input filter to a switching regulator leads to a modified control-to-output transfer function. The output impedance of the filter must be sufficiently small at point VB so that input filter does not significantly affect the loop gain of the SMPS.

The physics behind the warning: a regulated converter holds its output constant, so it draws constant power from its input. Raise the input voltage and the current falls — incrementally, the input looks like a negative resistance of magnitude V_in²/P_in. For the SNVA755 operating point, 24 V in and 15 W through at ideal efficiency, that is about 38 Ω. An undamped filter whose output impedance peaks near 7 Ω is already within a factor of six of it — 15 dB; component tolerance, a bigger L_f, or operation at a lower input voltage (which shrinks V_in²/P_in quadratically) closes the gap, and the two impedances interacting is an oscillator. The references AN-2162 points to for the full treatment are Middlebrook’s input-filter papers and Erickson’s Fundamentals of Power Electronics — the damping formulas above are the practical residue of that literature.

The rule that falls out: keep the filter’s output impedance well below the converter’s input impedance magnitude at every frequency, and check it at minimum input voltage and maximum load, where the converter side is smallest. The damped curve in Fig 9 clears it by more than a decade everywhere; the undamped one is a tolerance stack away from trouble.

Layout: what it fixes, and what it cannot

AN-2162 is blunt that layout does not fix conducted EMI — the discontinuous current exists because the topology switches, and no arrangement of copper changes the Fourier series. What layout controls is everything adjacent: whether the switching edges also radiate, and whether high-frequency noise couples around the filter you just designed. SNVA755 gives the mechanism:

The self-inductance of a current loop is proportional to the area enclosed by it. The loops containing high di/dt current are the critical paths in SMPS PCB design. To reduce the voltage spikes and switching noises in an SMPS, the critical high di/dt paths should be identified and the area enclosed by them should be minimized.

In a buck the critical loop is the input capacitor, the high-side switch and the low-side switch or diode — the loop that carries the discontinuous current. SNVA755’s placement rules follow directly: put the bypass capacitor as close as possible to the IC’s VIN and GND pins, connect it with short wide traces on the IC’s own layer, and avoid vias in the path — their parasitic inductance “will make the high frequency bypass ineffective”. Then let the plane do the shielding:

the ground plane at the mid-layer allows a mirror return current to be formed right underneath a top layer current. The mirror current path minimizes the current loop area and the magnetic field generated by the two opposite direction currents will be almost canceled.

The filter belongs at the point of entry, and the hot loop’s field is the reason: a filter placed inside the switching loop’s reach, or connected to it by long thin traces, can be bridged by exactly the coupling the plane exists to cancel. The payoff crosses test categories, too — AN-2162 observes that keeping conducted differential EMI in check above 30 MHz “will assist in meeting the separately tested radiated EMI requirements”, and SNVA755’s reference layout passed CISPR 22 Class B radiated limits with 10 dB of margin.

The worked example, end to end

SNVA755’s design, with every number from the note:

converter          LMR16030, 24 V in, 5 V / 3 A out
fs                 420 kHz
CIN                9.62 µF (ceramic)
required |Att|     45 dB            to pass CISPR 22 Class B
Lf                 12 µH            1234AS-H-120M (1 A, 0.19 Ω)

Cfa = CIN / (CIN·Lf·(2π·fs/10)² − 1)            = 1.37 µF
Cfb = (1/Lf) · (10^(45/40) / (2π·fs))²          = 2.1 µF
Cf  = 4.7 µF ∥ 0.22 µF                          (above both)

Cd  ≥ 4 × 9.62 µF ≈ 38 µF, ESRd ≈ √(Lf/CIN) ≈ 1.1 Ω
                                   (omitted on the board, for cost)

Running the model of this article over those values: corner at 21 kHz, 52 dB of attenuation at the fundamental against 45 required, and the note’s scans show the fundamental and harmonics “well suppressed” with the filter in place.

AN-2162’s first example makes the before/after arithmetic visible. The LMZ23605 board — 800 kHz, C_IN = 20 µF, estimated fundamental 80 dBµV against a 40 dBµV requirement — needs 40 dB. With L_f = 1 µH the formulas give C_fa = 4.9 µF and C_fb = 2.5 µF; the board uses 4.7 µF and a 150 µF damping capacitor. The computed response of that stage at 800 kHz is −41 dB:

The fundamental lands just under the line, and every harmonic falls further below it than the one before — the −40 dB/decade slope doing exactly what the “design at the fundamental” rule promised. AN-2162 closes the example with the honest caveat that “in most cases, the LC design will benefit from iteration”; the formulas put the first pass close, the LISN scan finishes the job.

The recipe

1. Find the required attenuation at the switching fundamental: from a LISN scan if one exists, else from the input ripple on a scope (Method 1) or the square-wave model (Method 2).
2. Pick L_f: 1–10 µH, the largest that meets the current rating and fits, rated for the DC input current.
3. Compute C_fa and C_fb, take the higher, round up to a standard value. The corner must sit at least a decade below f_s.
4. Damp it: C_d ≥ 4·C_IN, ESR_d ≈ √(L_f/C_IN), voltage rating 25 % above the maximum source voltage. An aluminium electrolytic is both parts at once.
5. Check the impedance overlap at minimum V_in and maximum load: filter output impedance well below V_in²/P_in everywhere.
6. Place the filter at the input connector, the bypass capacitor tight against the IC, the hot loop minimal, an unbroken plane underneath.
7. Scan, then iterate. The formulas are a first pass by design.

Sources

• TI SNVA489 — AN-2162 Simple Success With Conducted EMI From DC-DC Converters — the square-wave input current model, the two required-attenuation methods, the L_f/C_f/C_d design equations, both LMZ design examples, and the LISN chapter with its bench cautions.
• TI SNVA755 — Simple Success with Conducted and Radiated EMI for LMR160X0 — the same procedure applied to a 24 V/5 V/3 A LMR16030 design against CISPR 22 Class B, with the component values used here, plus the hot-loop and ground-plane layout rules for the radiated half of the problem.

Updates

• 2026-09-13 — Corrected the filter topology: Cf sits on the source side (VA) of Lf, with only the damping branch and CIN on VB, as in AN-2162 Figure 4 and SNVA755 Figure 4. Figs 5, 8 and 10 redrawn, and the text on the design direction and the Cfa formula reworded to match.
• 2026-09-13 — Rebuilt the output-impedance model of Figs 7 and 9 around Lf and CIN, the resonance AN-2162 §4.4 actually damps; the earlier model resonated Lf against Cf and left CIN out. The undamped peak is 6.7 Ω near 15 kHz (was given as 13 Ω), the damped peak 1.0 Ω (was 1.5 Ω), and the margin to the converter’s 38 Ω is 15 dB, not 9 dB.
• 2026-09-13 — Fig 6 annotation and text: the 21 kHz corner is more than a decade below fs, not exactly one.