Dropout voltage: why the datasheet number is not yours

Dropout voltage is the smallest difference between an LDO’s input and its output at which it still regulates. TI’s definitions note says it exactly:

Dropout voltage is the input-to-output differential voltage at which the circuit ceases to regulate against further reductions in input voltage; this point occurs when the input voltage approaches the output voltage.

— TI, SLVA079

A 3.3 V regulator with 350 mV of dropout needs 3.65 V at its input. Give it less and it does not switch off; it stops being a regulator and becomes a resistor, and the output “will track V_IN minus the dropout voltage” (TI’s LDO Basics article). That is the whole definition, and it leaves out the part that catches people: the number in the datasheet was measured at one current, usually the rated maximum, and at any other current it is different. Dropout is a resistance. TI’s SLVA207 turns a specified 160 mV at 200 mA into 0.8 Ω and reads 80 mV at 100 mA off the same line; the LDO dropout calculator does that arithmetic for any part and checks it against the lowest input the rail ever reaches. This article is what the number means and where it comes from.

The pass element is a resistor

An LDO regulates by controlling the resistance of a transistor in series with the load. SLVA207 describes the operating point on the FET’s V-I curve: with 5 V in, 3.3 V out and 500 mA, the FET is being held at 1.7 V / 0.5 A = 3.4 Ω. As the input falls the loop lowers that resistance to keep the output where it is. At some point the gate drive runs out:

The FET has a minimum resistance that is shown by the Saturation Line in Figure 1. If the circuit conditions require that the FET operate with a lower resistance than the Saturation Line allows, the LDO is in dropout.

— TI, SLVA207

In its example that floor is 0.8 Ω: at 4 V in and 700 mA the FET needs 2.4 Ω and is fine; at 3.8 V it would need 0.71 Ω, “but it can not go any lower than 0.8 Ω. The LDO is now operating in dropout.” SLVA079 says the same in one line — “in the dropout region, the PMOS pass element is simply a resistor” — and writes the dropout as I_O × R_on.

That is why the dropout has a current attached to it. The TPS76733 in SLVA079’s example is “typically 350 mV at 1 A”; the TPS799 in TI’s LDO Basics article is “specified at 175 mV” maximum “when sourcing 200 mA”. Halve the current and the same transistor drops half the voltage.

Scaling the datasheet number to your load

SLVA207 exists because “dropout is usually only specified at the LDO’s maximum rated output current”, and the graphs of dropout against current that some datasheets add “only contain typical data that is not specified”. Its procedure is two lines:

$R_{on} = \frac{V_{DO(spec)}}{I_{test}} \qquad\qquad V_{DO} = R_{on} \times I_{load}$

For the TPS79901 at 3.3 V: 160 mV at 200 mA is 0.8 Ω, so “if an application requires 100 mA from this LDO, the specified dropout voltage is 0.8 Ω × 100 mA = 80 mV”. The note adds that this is “slightly higher than the typical dropout voltage” on the graph, which is the point: the line from the origin through the specified maximum is a specified number, and the graph is not.

Two cautions come with the line. It runs from zero up to the test current and no further; above the rated current the FET is not specified at all. And it is a line at one temperature. SLVA207’s TPS799 curves run from −40 to 125 °C and the dropout roughly doubles across them, so the figure to scale is the maximum over the temperature range the junction will actually reach — which the dissipation, below, decides.

Where the resistance comes from: PMOS and NMOS

TI’s LDO Basics article explains why the floor is where it is. In a PMOS LDO the error amplifier drives the gate toward ground to lower R_DS; “at a certain point, however, the error-amplifier output will saturate at ground and cannot drive V_GS more negative. R_DS has reached its minimum value.” Because V_GS is measured from the input, a higher input gives a more negative V_GS and a lower resistance: “PMOS architectures will have lower dropout at higher output voltages.” The 1.2 V option of a PMOS LDO has worse dropout than its 3.3 V option, which is why datasheets tabulate them separately.

An NMOS pass element is the other way round. Its gate must be driven above the output, and “as V_IN approaches V_OUT(nom), V_GS will also decrease, since the error-amplifier output saturates at V_IN. This prevents ultra-low dropout.” The fix is to give the amplifier a rail above the input — an external bias voltage, or an internal charge pump that “will boost V_IN so that the error amplifier may generate a larger V_GS value”. An NMOS LDO with a bias pin has its dropout specified with the bias present; without it, the part is not the part in the table.

Checking headroom at the floor, not the nominal

The check is at the lowest input the LDO will ever see: the rail’s tolerance floor, a battery near empty, the far end of a cable. TI’s LDO Basics example shows what happens at the wrong side of it:

As long as the input voltage is 3.475 V or greater, regulation is not affected. However, dropping the input voltage to 3.375 V will cause the LDO to enter dropout operation and cease regulation.

— TI, SSZTAC2

At 3.375 V the 3.3 V TPS799 delivers 3.2 V: the input minus the dropout. Nothing in the system reports that; the microcontroller behind it runs at 3.2 V until something depending on a 3.3 V reference is out of tolerance. The margin to leave depends on how well the floor is known. The dropout figure itself is a maximum, but at a temperature; the floor has a tolerance of its own; and a load step at the floor takes what static margin there is for the duration of the transient.

What headroom costs

The other end of the input range asks the opposite question. Everything above the knee is dropped across the pass element at the load current:

$P_D = (V_{IN} - V_{OUT}) \times I_O$

SLVA079 writes the efficiency as I_OV_O over (I_O + I_Q)V_I and says plainly that “the input/output voltage difference is an intrinsic factor in determining the efficiency, regardless of the load conditions”. Its worked example is 100 mA at 3.3 V with 17 mA of quiescent current from a 4.5 V input, for which it prints 73.3 %, and 82.5 % from 4 V. Those are 3.3/4.5 and 3.3/4 — the expression with the quiescent current left out of the denominator. With the 17 mA included, as the formula is written, the figures are 62.7 % and 70.5 %. The calculator uses the formula as written; the difference is worth knowing because a 17 mA quiescent current is not small against a 100 mA load, and neither is the difference between the two answers.

The maximum the package can dissipate is SLVA079’s other equation, (T_J,max − T_A) / R_θJA, and the LDO thermal calculator is where that check lives. The two calculators are the two ends of the same input range.

Worked numbers

The calculator’s defaults: TI’s TPS799 figure, a 150 mA load, a rail specified 3.6–5.5 V.

datasheet         175 mV max at 200 mA, 3.3 V out       R_on = 0.875 Ω
at 150 mA         V_DO = 0.875 × 0.15                   = 131 mV
input needed      3.3 + 0.131                           = 3.431 V
headroom          3.6 − 3.431                           = 169 mV
dissipation       (3.6 − 3.3) × 0.15                    = 45 mW at the floor
                  (5.5 − 3.3) × 0.15                    = 330 mW at the ceiling
efficiency        3.3 / 3.6 and 3.3 / 5.5               = 91.7 % and 60.0 %  (I_Q = 0)
floor could feed  (3.6 − 3.3) / 0.875                   = 343 mA before dropout

the same part at 200 mA from 3.375 V  (SSZTAC2's case)
                  V_DO = 175 mV, needs 3.475 V           → 100 mV short, output 3.2 V

Dropout is checked at the floor with the real load, dissipation at the ceiling, and the datasheet figure is a resistance to be scaled before it is either.